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MCF51QE128 MCU Series Reference Manual, Rev. 3
Freescale Semiconductor 95
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Chapter 5 Resets, Interrupts, and General System Control
5.3.2 Illegal Operation Reset
By default, the V1 ColdFire core generates a MCU reset when attempting to execute an illegal instruction
(except for the ILLEGAL opcode), illegal line-A instruction, illegal line-F instruction, or a supervisor
instruction while in user mode (privilege violation). The user may set CPUCR[IRD] to generate the
appropriate exception instead of forcing a reset.
NOTE
The attempted execution of the STOP instruction with SOPT[STOPE,
WAITE] cleared is treated as an illegal instruction.
The attempted execution of the HALT instruction with XCSR[ENBDM]
cleared is treated as an illegal instruction.
5.3.3 Illegal Address Reset
By default, the V1 ColdFire core generates a MCU reset when detecting an address error, bus error
termination, RTE format error, or fault-on-fault condition. The user may set CPUCR[ARD] to generate the
appropriate exception instead of forcing a reset, or simply halt the processor in response to the
fault-on-fault condition.
5.4 Interrupts and Exceptions
The interrupt architecture of ColdFire utilizes a 3-bit encoded interrupt priority level sent from the
interrupt controller to the core, providing seven levels of interrupt requests. Level seven represents the
highest priority interrupt level, while level one is the lowest priority. For more information on exception
processing, see Chapter 8, “Interrupt Controller (CF1_INTC)”.
5.4.1 External Interrupt Request (IRQ) Pin
External interrupts are managed by the IRQ status and control register, IRQSC. When the IRQ function is
enabled, synchronous logic monitors the pin for edge-only or edge-and-level events. When the MCU is in
stop mode and system clocks are shut down, a separate asynchronous path is used, so the IRQ pin (if
enabled) can wake the MCU.
5.4.1.1 Pin Configuration Options
The IRQ pin enable (IRQPE) control bit in IRQSC must be set for the IRQ pin to act as the interrupt request
(IRQ) input. As an IRQ input, you can choose the polarity of edges or levels detected (IRQEDG), whether
the pin detects edges-only or edges and levels (IRQMOD) and whether an event causes an interrupt or only
sets the IRQF flag that can be polled by software (IRQIE).
The IRQ pin, when enabled, defaults to use an internal pull device (IRQPDD = 0), configured as a pull-up
or pull-down depending on the polarity chosen. If you want to use an external pull-up or pull-down, the
IRQPDD can be set to turn off the internal device.