Filter
Top Products
Internal Clock Source (S08ICSV3)
MCF51QE128 MCU Series Reference Manual, Rev. 3
Freescale Semiconductor 257
Get the latest version from freescale.com
12.4.4 Low Power Bit Usage
The low-power bit (LP) is provided to allow the FLL to be disabled and conserve power when it is not
being used. The DRS bits can not be written while LP bit is 1.
However, in some applications, it may be desirable to allow the FLL to be enabled and to lock for
maximum accuracy before switching to an FLL engaged mode. Do this by writing the LP bit to 0.
12.4.5 DCO Maximum Frequency with 32.768 kHz Oscillator
The FLL has an option to change the clock multiplier for the selected DCO range so it results in the
maximum bus frequency with a common 32.768 kHZ crystal reference clock.
12.4.6 Internal Reference Clock
When IRCLKEN is set, the internal reference clock signal is presented as ICSIRCLK, which can be used
as an additional clock source. The ICSIRCLK frequency can be re-targeted by trimming the period of the
internal reference clock. This can be done by writing a new value to the TRIM bits in the ICSTRM register.
Writing a larger value slows down the ICSIRCLK frequency, and writing a smaller value to the ICSTRM
register speeds up the ICSIRCLK frequency. The TRIM bits affect the ICSOUT frequency if the ICS is in
FLL engaged internal (FEI), FLL bypassed internal (FBI), or FLL bypassed internal low-power (FBILP)
mode.
Until ICSIRCLK is trimmed, programming low reference divider (RDIV) factors may result in ICSOUT
frequencies that exceed the maximum chip-level frequency and violate the chip-level clock timing
specifications (see the Device Overview chapter).
If IREFSTEN is set and the IRCLKEN bit is written to 1, the internal reference clock keeps running during
stop mode to provide a fast recovery upon exiting stop.
All MCU devices are factory programmed with a trim value in a reserved memory location. This value is
uploaded to the ICSTRM register and ICS FTRIM register during any reset initialization. For finer
precision, you can trim the internal oscillator in the application and set the FTRIM bit accordingly.
12.4.7 External Reference Clock
The ICS module supports an external reference clock with frequencies between 31.25 kHz to 40 MHz in
all modes. When the ERCLKEN is set, the external reference clock signal is presented as ICSERCLK,
which can be used as an additional clock source. When IREFS is set, the external reference clock is not
used by the FLL and is only used as ICSERCLK. In these modes, the frequency can be equal to the
maximum frequency the chip-level timing specifications support (see the Device Overview chapter).
If EREFSTEN is set and the ERCLKEN bit is written to 1, the external reference clock keeps running
during stop mode to provide a fast recovery upon exiting stop.