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MCF51QE128 MCU Series Reference Manual, Rev. 3
Freescale Semiconductor 11
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Section Number Title Page
6.7.4.2 Port D Data Direction Register (PTDDD) ....................................................127
6.7.4.3 Port D Pull Enable Register (PTDPE) ..........................................................127
6.7.4.4 Port D Slew Rate Enable Register (PTDSE) ................................................128
6.7.4.5 Port D Drive Strength Selection Register (PTDDS) .....................................128
6.7.5 Port E Registers ..............................................................................................................128
6.7.5.1 Port E Data Register (PTED) ........................................................................128
6.7.5.2 Port E Data Direction Register (PTEDD) .....................................................129
6.7.5.3 Port E Data Set Register (PTESET) ..............................................................129
6.7.5.4 Port E Data Clear Register (PTECLR) .........................................................130
6.7.5.5 Port E Toggle Register (PTETOG) ...............................................................130
6.7.5.6 Port E Pull Enable Register (PTEPE) ...........................................................130
6.7.5.7 Port E Slew Rate Enable Register (PTESE) .................................................131
6.7.5.8 Port E Drive Strength Selection Register (PTEDS) ......................................131
6.7.6 Port F Registers ...............................................................................................................132
6.7.6.1 Port F Data Register (PTFD) ........................................................................132
6.7.6.2 Port F Data Direction Register (PTFDD) .....................................................132
6.7.6.3 Port F Pull Enable Register (PTFPE) ............................................................132
6.7.6.4 Port F Slew Rate Enable Register (PTFSE) ..................................................133
6.7.6.5 Port F Drive Strength Selection Register (PTFDS) ......................................133
6.7.7 Port G Registers ..............................................................................................................134
6.7.7.1 Port G Data Register (PTGD) .......................................................................134
6.7.7.2 Port G Data Direction Register (PTGDD) ....................................................134
6.7.7.3 Port G Pull Enable Register (PTGPE) ..........................................................135
6.7.7.4 Port G Slew Rate Enable Register (PTGSE) ................................................135
6.7.7.5 Port G Drive Strength Selection Register (PTGDS) .....................................135
6.7.8 Port H Registers ..............................................................................................................136
6.7.8.1 Port H Data Register (PTHD) .......................................................................136
6.7.8.2 Port H Data Direction Register (PTHDD) ....................................................136
6.7.8.3 Port H Pull Enable Register (PTHPE) ..........................................................137
6.7.8.4 Port H Slew Rate Enable Register (PTHSE) ................................................137
6.7.8.5 Port H Drive Strength Selection Register (PTHDS) .....................................137
6.7.9 Port J Registers ...............................................................................................................138
6.7.9.1 Port J Data Register (PTJD) ..........................................................................138
6.7.9.2 Port J Data Direction Register (PTJDD) .......................................................138
6.7.9.3 Port J Pull Enable Register (PTJPE) .............................................................139
6.7.9.4 Port J Slew Rate Enable Register (PTJSE) ...................................................139
6.7.9.5 Port J Drive Strength Selection Register (PTJDS) ........................................139
6.7.10 Keyboard Interrupt 1 (KBI1) Registers ..........................................................................140
6.7.10.1 KBI1 Interrupt Status and Control Register (KBI1SC) ................................140
6.7.10.2 KBI1 Interrupt Pin Select Register (KBI1PE) ..............................................141
6.7.10.3 KBI1 Interrupt Edge Select Register (KBI1ES) ...........................................141
6.7.11 Keyboard Interrupt 1 (KBI2) Registers ..........................................................................141