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MCF51QE128 MCU Series Reference Manual, Rev. 3
Freescale Semiconductor 13
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Section Number Title Page
7.3.4.5 Miscellaneous Instruction Execution Times .................................................171
7.3.4.6 Branch Instruction Execution Times .............................................................172
Chapter 8
Interrupt Controller (CF1_INTC)
8.1 Introduction ...................................................................................................................................173
8.1.1 Overview .........................................................................................................................174
8.1.2 Features ...........................................................................................................................177
8.1.3 Modes of Operation ........................................................................................................178
8.2 External Signal Description ..........................................................................................................178
8.3 Memory Map and Register Definition ..........................................................................................178
8.3.1 Memory Map ..................................................................................................................179
8.3.2 Register Descriptions ......................................................................................................179
8.3.2.1 INTC Force Interrupt Register (INTC_FRC) ...............................................179
8.3.2.2 INTC Programmable Level 6, Priority {7,6} Registers (INTC_PL6P{7,6}) .....
180
8.3.2.3 INTC Wake-up Control Register (INTC_WCR) ..........................................181
8.3.2.4 INTC Set Interrupt Force Register (INTC_SFRC) .......................................182
8.3.2.5 INTC Clear Interrupt Force Register (INTC_CFRC) ...................................183
8.3.2.6 INTC Software and Level-n IACK Registers (n = 1,2,3,...,7) ......................184
8.3.3 Interrupt Request Level and Priority Assignments .........................................................185
8.4 Functional Description ..................................................................................................................187
8.4.1 Handling of Non-Maskable Level 7 Interrupt Requests .................................................187
8.5 Initialization Information ..............................................................................................................188
8.6 Application Information ................................................................................................................188
8.6.1 Emulation of the HCS08’s 1-Level IRQ Handling .........................................................188
8.6.2 Using INTC_PL6P{7,6} Registers .................................................................................189
8.6.3 More on Software IACKs ...............................................................................................189
Chapter 9
Rapid GPIO (RGPIO)
9.1 Introduction ...................................................................................................................................193
9.1.1 Overview .........................................................................................................................195
9.1.2 Features ...........................................................................................................................197
9.1.3 Modes of Operation ........................................................................................................198
9.2 External Signal Description ..........................................................................................................198
9.2.1 Overview .........................................................................................................................198
9.2.2 Detailed Signal Descriptions ..........................................................................................198
9.3 Memory Map/Register Definition .................................................................................................199
9.3.1 Memory Map ..................................................................................................................199
9.3.2 Register Descriptions ......................................................................................................200
9.3.2.1 RGPIO Data Direction (RGPIO_DIR) .........................................................200