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MCF51QE128 MCU Series Reference Manual, Rev. 3
Freescale Semiconductor 199
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Chapter 9 Rapid GPIO (RGPIO)
9.3 Memory Map/Register Definition
The RGPIO module provides a compact 16-byte programming model based at a system memory address
of 0x(00)C0_0000 (noted as RGPIO_BASE throughout the chapter). As previously noted, the
programming model views are different between reads and writes as this enables simplified software for
manipulation of the RGPIO pins. Additionally, the programming model can be referenced using any
operand size access (byte, word, longword).
9.3.1 Memory Map
The RGPIO programming model maps are shown in Table 9-3 and Table 9-4.
NOTE
Writes to the 2-byte fields at RGPIO_BASE + 0x8 and
RGPIO_BASE + 0xC are allowed, but do not affect any program-visible
register within the RGPIO module.
Table 9-3. RGPIO Write Memory Map
Offset
Address
Register
Width
(bits)
Access Reset Value Section/Page
0x0 RGPIO Data Direction Register (RGPIO_DIR) 16 W 0x0000 9.3.2.1/9-200
0x2 RGPIO Write Data Register (RGPIO_DATA) 16 W 0x0000 9.3.2.2/9-200
0x4 RGPIO Pin Enable Register (RGPIO_ENB) 16 W 0x0000 9.3.2.3/9-201
0x6 RGPIO Write Data Clear Register (RGPIO_CLR) 16 W N/A 9.3.2.4/9-201
0xA RGPIO Write Data Set Register (RGPIO_SET) 16 W N/A 9.3.2.5/9-202
0xE RGPIO Write Data Toggle Register (RGPIO_TOG) 16 W N/A 9.3.2.6/9-202
Table 9-4.
RGPIO Read Memory Map
Offset
Address
Register
Width
(bits)
Access Reset Value Section/Page
0x0 RGPIO data direction register (RGPIO_DIR) 16 R 0x0000 9.3.2.1/9-200
0x2 RGPIO write data register (RGPIO_DATA) 16 R 0x0000 9.3.2.2/9-200
0x4 RGPIO pin enable register (RGPIO_ENB) 16 R 0x0000 9.3.2.3/9-201
0x6 RGPIO write data register (RGPIO_DATA) 16 R 0x0000 9.3.2.2/9-200
0x8 RGPIO data direction register (RGPIO_DIR) 16 R 0x0000 9.3.2.1/9-200
0xA RGPIO write data register (RGPIO_DATA) 16 R 0x0000 9.3.2.2/9-200
0xC RGPIO data direction register (RGPIO_DIR) 16 R 0x0000 9.3.2.1/9-200
0xE RGPIO write data register (RGPIO_DATA) 16 R 0x0000 9.3.2.2/9-200