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MCF51QE128 MCU Series Reference Manual, Rev. 3
Freescale Semiconductor 93
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Chapter 5
Resets, Interrupts, and General System Control
5.1 Introduction
This section discusses basic reset and interrupt mechanisms and the various sources of reset and interrupt
on the MCF51QE128/64/32. Some interrupt sources from peripheral modules are discussed in greater
detail within other sections of this document. This section gathers basic information about all reset and
interrupt sources in one place for easy reference. A few reset and interrupt sources, including the computer
operating properly (COP) watchdog, are not part of on-chip peripheral systems with their own chapters.
5.2 Features
Reset and interrupt features include:
• Multiple sources of reset for flexible system configuration and reliable operation
• System reset status (SRS) register to indicate source of most recent reset
• Separate interrupt vector for most modules (reduces polling overhead)
5.3 Microcontroller Reset
Resetting the MCU provides a way to start processing from a known set of initial conditions. When the
ColdFire processor exits reset, it fetches initial 32-bit values for the supervisor stack pointer and program
counter from locations 0x(00)00_0000 and 0x(00)00_0004 respectively. On-chip peripheral modules are
disabled and I/O pins are initially configured as general-purpose high-impedance inputs with pull-up
devices disabled.
The MCF51QE128/64/32 has the following sources for reset:
• Power-on reset (POR)
• External pin reset (PIN)
• Computer operating properly (COP) timer
• Illegal opcode detect (ILOP)
• Illegal address detect (ILAD)
• Low-voltage detect (LVD)
• Background debug forced reset
Each of these sources, with the exception of the background debug forced reset, has an associated bit in
the system reset status register (SRS).