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ColdFire Core
MCF51QE128 MCU Series Reference Manual, Rev. 3
Freescale Semiconductor 161
In the original M68000 ISA definition, lines A and F were effectively reserved for user-defined operations
(line A) and co-processor instructions (line F). Accordingly, there are two unique exception vectors
associated with illegal opwords in these two lines.
Any attempted execution of an illegal 16-bit opcode (except for line-A and line-F opcodes) generates an
illegal instruction exception (vector 4). Additionally, any attempted execution of any line-A and most
line-F opcodes generate their unique exception types, vector numbers 10 and 11, respectively. ColdFire
cores do not provide illegal instruction detection on the extension words on any instruction, including
MOVEC.
The V1 ColdFire processor also detects two special cases involving illegal instruction conditions:
1. If execution of the stop instruction is attempted and neither low-power stop nor wait modes are
enabled, the processor signals an illegal instruction.
2. If execution of the halt instruction is attempted and BDM is not enabled
(XCSR[ENBDM] equals 0), the processor signals an illegal instruction.
In both cases, the processor response is then dependent on the state of CPUCR[IRD]— a reset event or a
processor exception.
7.3.3.4 Privilege Violation
The default operation of the V1 ColdFire processor is the generation of an illegal opcode reset event if a
privilege violation is detected. If CPUCR[IRD] is set, the reset is disabled and a processor exception is
generated as detailed below.
The attempted execution of a supervisor mode instruction while in user mode generates a privilege
violation exception. See ColdFire Programmer’s Reference Manual for a list of supervisor-mode
instructions.
There is one special case involving the HALT instruction. Normally, this opcode is a supervisor mode
instruction, but if the debug module's CSR[UHE] is set, then this instruction can be also be executed in
user mode for debugging purposes.
7.3.3.5 Trace Exception
To aid in program development, all ColdFire processors provide an instruction-by-instruction tracing
capability. While in trace mode, indicated by setting of the SR[T] bit, the completion of an instruction
execution (for all but the stop instruction) signals a trace exception. This functionality allows a debugger
to monitor program execution.
The stop instruction has the following effects:
1. The instruction before the stop executes and then generates a trace exception. In the exception stack
frame, the PC points to the stop opcode.
2. When the trace handler is exited, the stop instruction executes, loading the SR with the immediate
operand from the instruction.
3. The processor then generates a trace exception. The PC in the exception stack frame points to the
instruction after the stop, and the SR reflects the value loaded in the previous step.