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Analog-to-Digital Converter (S08ADC12V1)
MCF51QE128 MCU Series Reference Manual, Rev. 3
Freescale Semiconductor 221
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11.2.1 Analog Power (V
DDAD
)
The ADC analog portion uses V
DDAD
as its power connection. In some packages, V
DDAD
is connected
internally to V
DD
. If externally available, connect the V
DDAD
pin to the same voltage potential as V
DD
.
External filtering may be necessary to ensure clean V
DDAD
for good results.
11.2.2 Analog Ground (V
SSAD
)
The ADC analog portion uses V
SSAD
as its ground connection. In some packages, V
SSAD
is connected
internally to V
SS
. If externally available, connect the V
SSAD
pin to the same voltage potential as V
SS
.
11.2.3 Voltage Reference High (V
REFH
)
V
REFH
is the high reference voltage for the converter. In some packages, V
REFH
is connected internally to
V
DDAD
. If externally available, V
REFH
may be connected to the same potential as V
DDAD
or may be driven
by an external source between the minimum V
DDAD
spec and the V
DDAD
potential (V
REFH
must never
exceed V
DDAD
).
11.2.4 Voltage Reference Low (V
REFL
)
V
REFL
is the low-reference voltage for the converter. In some packages, V
REFL
is connected internally to
V
SSAD
. If externally available, connect the V
REFL
pin to the same voltage potential as V
SSAD
.
11.2.5 Analog Channel Inputs (ADx)
The ADC module supports up to 28 separate analog inputs. An input is selected for conversion through
the ADCH channel select bits.
11.3 Register Definition
These memory-mapped registers control and monitor operation of the ADC:
• Status and control register, ADCSC1
• Status and control register, ADCSC2
• Data result registers, ADCRH and ADCRL
• Compare value registers, ADCCVH and ADCCVL
• Configuration register, ADCCFG
• Pin enable registers, APCTL1, APCTL2, APCTL3
11.3.1 Status and Control Register 1 (ADCSC1)
This section describes the function of the ADC status and control register (ADCSC1). Writing ADCSC1
aborts the current conversion and initiates a new conversion (if the ADCH bits are equal to a value other
than all 1s).