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MCF51QE128 MCU Series Reference Manual, Rev. 3
Freescale Semiconductor 145
Chapter 7
ColdFire Core
7.1 Introduction
This section describes the organization of the Version 1 (V1) ColdFire
®
processor core and an overview
of the program-visible registers. For detailed information on instructions, see the ISA_C definition in the
ColdFire Family Programmer’s Reference Manual.
7.1.1 Overview
As with all ColdFire cores, the V1 ColdFire core is comprised of two separate pipelines decoupled by an
instruction buffer.
Figure 7-1. V1 ColdFire Core Pipelines
The instruction fetch pipeline (IFP) is a two-stage pipeline for prefetching instructions. The prefetched
instruction stream is then gated into the two-stage operand execution pipeline (OEP), which decodes the
Instruction
Instruction
FIFO
Decode & Select,
Address
IAG
IC
IB
DSOC
AGEX
Instruction Buffer
Address
Generation
Fetch Cycle
Generation,
Execute
Operand Fetch
Instruction
Operand
Pipeline
Execution
Fetch
Pipeline
Address [23:0]
Read Data[31:0]
Write Data[31:0]