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MCF51QE128 MCU Series Reference Manual, Rev. 3
Freescale Semiconductor 327
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Figure 16-10. SPI Clock Formats (CPHA = 1)
When CPHA is set, the slave begins to drive its MISO output when SS asserts, but the data is not defined
until the first SPSCK edge. The first SPSCK edge shifts the first bit of data from the shifter onto the MOSI
output of the master and the MISO output of the slave. The next SPSCK edge causes the master and the
slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the third SPSCK edge,
the SPI shifter shifts one bit position that shifts in the bit value that was sampled, and shifts the second data
bit value out the other end of the shifter to the MOSI and MISO outputs of the master and slave,
respectively. When CHPA is set, the slave’s SS
input is not required to negate between transfers.
Figure 16-11 shows the clock formats when CPHA is cleared. At the top of the figure, the eight bit times
are shown for reference with bit 1 starting as the slave is selected (SS IN asserts), and bit 8 ends at the last
SPSCK edge. The msb first and lsb first lines show the order of SPI data bits depending on the setting of
SPIxC1[LSBFE]. Both variations of SPSCK polarity are shown, but only one of these waveforms applies
for a specific transfer, depending on the value in CPOL. The SAMPLE IN waveform applies to the MOSI
input of a slave or the MISO input of a master. The MOSI waveform applies to the MOSI output pin from
a master and the MISO waveform applies to the MISO output from a slave. The SS OUT waveform applies
to the slave select output from a master (provided MODFEN and SSOE are set). The master SS
output
asserts at the start of the first bit time of the transfer and negates one-half SPSCK cycle after the end of the
eighth bit time of the transfer. The SS
IN waveform applies to the slave select input of a slave.
Bit Time #
(REFERENCE)
msb FIRST
lsb FIRST
SPSCK
(CPOL = 0)
SPSCK
(CPOL = 1)
SAMPLE IN
(MISO OR MOSI)
MOSI
(MASTER OUT)
MISO
(SLAVE OUT)
SS
OUT
(MASTER)
SS
IN
(SLAVE)
BIT 7
BIT 0
BIT 6
BIT 1
BIT 2
BIT 5
BIT 1
BIT 6
BIT 0
BIT 7
12 67 8
...
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