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MCF51QE128 MCU Series Reference Manual, Rev. 3
Freescale Semiconductor 313
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Chapter 16
Serial Peripheral Interface (S08SPIV3)
16.1 Introduction
Figure 16-1 shows the MCF51QE128 Series block diagram with the SPI highlighted.
NOTE
Ignore any references to stop1 low-power mode in this chapter, because the
MCF51QE128 device does not support it.
16.1.1 SPI Clock Gating
The bus clock to SPI1 and SPI2 can be gated on and off using the SPI1 and SPI2 bits, respectively, in
SCGC2. These bits are set after any reset, which enables the bus clock to this module. To conserve power,
these bits can be cleared to disable the clock to either of these modus when not in use. See Section 5.6,
“Peripheral Clock Gating,” for details.
16.1.2 Interrupt Vector
See Chapter 8, “Interrupt Controller (CF1_INTC),” for the SPI interrupt vector assignments.