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MCF51QE128 MCU Series Reference Manual, Rev. 3
Freescale Semiconductor 139
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Chapter 6 Parallel Input/Output Control
6.7.9.3 Port J Pull Enable Register (PTJPE)
The port J pull enable register enables pull-ups on the corresponding PTJ pin. In some cases, a pull-down
device is enabled if pull-downs are supported by an alternate pin function (e.g., KBI).
6.7.9.4 Port J Slew Rate Enable Register (PTJSE)
6.7.9.5 Port J Drive Strength Selection Register (PTJDS)
76543210
R
PTJPE7 PTJPE6 PTJPE5 PTJPE4 PTJPE3 PTJPE2 PTJPE1 PTJPE0
W
Reset:00000000
Figure 6-52. Internal Pull Enable for Port J Register (PTJPE)
Table 6-49. PTJPE Register Field Descriptions
Field Description
7–0
PTJPEn
Internal Pull Enable for Port J Bits. Each of these control bits determines if the internal pull-up device is enabled
for the associated PTJ pin. For port J pins configured as outputs, these bits have no effect and the internal pull
devices are disabled.
0 Internal pull-up device disabled for port J bit n.
1 Internal pull-up device enabled for port J bit n.
76543210
R
PTJSE7 PTJSE6 PTJSE5 PTJSE4 PTJSE3 PTJSE2 PTJSE1 PTJSE0
W
Reset:00000000
Figure 6-53. Slew Rate Enable for Port J Register (PTJSE)
Table 6-50. PTJSE Register Field Descriptions
Field Description
7–0
PTJSEn
Output Slew Rate Enable for Port J Bits. Each of these control bits determines if the output slew rate control is
enabled for the associated PTJ pin. For port J pins configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port J bit n.
1 Output slew rate control enabled for port J bit n.
76543210
R
PTJDS7 PTJDS6 PTJDS5 PTJDS4 PTJDS3 PTJDS2 PTJDS1 PTJDS0
W
Reset:00000000
Figure 6-54. Drive Strength Selection for Port J Register (PTJDS)