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Analog-to-Digital Converter (S08ADC12V1)
MCF51QE128 MCU Series Reference Manual, Rev. 3
238 Freescale Semiconductor
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For proper conversion, the input voltage must fall between V
REFH
and V
REFL
. If the input is equal to or
exceeds V
REFH
, the converter circuit converts the signal to 0xFFF (full scale 12-bit representation), 0x3FF
(full scale 10-bit representation) or 0xFF (full scale 8-bit representation). If the input is equal to or less
than V
REFL
,
the converter circuit converts it to 0x000. Input voltages between V
REFH
and V
REFL
are
straight-line linear conversions. There is a brief current associated with V
REFL
when the sampling
capacitor is charging. The input is sampled for 3.5 cycles of the ADCK source when ADLSMP is low, or
23.5 cycles when ADLSMP is high.
For minimal loss of accuracy due to current injection, pins adjacent to the analog input pins should not be
transitioning during conversions.
11.6.2 Sources of Error
Several sources of error exist for A/D conversions. These are discussed in the following sections.
11.6.2.1 Sampling Error
For proper conversions, the input must be sampled long enough to achieve the proper accuracy. Given the
maximum input resistance of approximately 7kΩ and input capacitance of approximately 5.5 pF, sampling
to within 1/4LSB (at 12-bit resolution) can be achieved within the minimum sample window (3.5 cycles @
8 MHz maximum ADCK frequency) provided the resistance of the external analog source (R
AS
) is kept
below 2 kΩ.
Higher source resistances or higher-accuracy sampling is possible by setting ADLSMP (to increase the
sample window to 23.5 cycles) or decreasing ADCK frequency to increase sample time.
11.6.2.2 Pin Leakage Error
Leakage on the I/O pins can cause conversion error if the external analog source resistance (R
AS
) is high.
If this error cannot be tolerated by the application, keep R
AS
lower than V
DDAD
/(2
N
*I
LEAK
) for less than
1/4LSB leakage error (N = 8 in 8-bit, 10 in 10-bit or 12 in 12-bit mode).
11.6.2.3 Noise-Induced Errors
System noise that occurs during the sample or conversion process can affect the accuracy of the
conversion. The ADC accuracy numbers are guaranteed as specified only if the following conditions are
met:
• There is a 0.1 μF low-ESR capacitor from V
REFH
to V
REFL
.
• There is a 0.1 μF low-ESR capacitor from V
DDAD
to V
SSAD
.
• If inductive isolation is used from the primary supply, an additional 1 μF capacitor is placed from
V
DDAD
to V
SSAD
.
•V
SSAD
(and V
REFL
, if connected) is connected to V
SS
at a quiet point in the ground plane.
• Operate the MCU in wait or stop3 mode before initiating (hardware triggered conversions) or
immediately after initiating (hardware or software triggered conversions) the ADC conversion.
— For software triggered conversions, immediately follow the write to ADCSC1 with a stop
instruction.