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ColdFire Core
MCF51QE128 MCU Series Reference Manual, Rev. 3
Freescale Semiconductor 149
To support dual stack pointers, the following two supervisor instructions are included in the ColdFire
instruction set architecture to load/store the USP:
move.l Ay,USP;move to USP
move.l USP,Ax;move from USP
These instructions are described in the ColdFire Family Programmer’s Reference Manual. All other
instruction references to the stack pointer, explicit or implicit, access the active A7 register.
NOTE
The USP must be initialized using the move.l Ay,USP instruction before any
entry into user mode.
The SSP is loaded during reset exception processing with the contents of
location 0x(00)00_0000.
Figure 7-4. Stack Pointer Registers (A7 and OTHER_A7)
7.2.4 Condition Code Register (CCR)
The CCR is the LSB of the processor status register (SR). Bits 4–0 act as indicator flags for results
generated by processor operations. The extend bit (X) is also an input operand during multiprecision
arithmetic computations. The CCR register must be explicitly loaded after reset and before any compare
(CMP), Bcc, or Scc instructions are executed.
BDM: Load: 0x6F (A7)
Store: 0x4F (A7)
Load: 0xE0 (OTHER_A7)
Store: 0xC0 (OTHER_A7)
Access: A7: User or BDM read/write
OTHER_A7: Supervisor or BDM read/write
313029282726252423222120191817161514131211109876543210
R
Address
W
Reset––––––––––––––––––––––––––––––––
BDM: LSB of Status Register (SR)
Load: 0xEE (SR)
Store: 0xCE (SR)
Access: User read/write
BDM read/write
76543210
R 0 0 0
X N Z V C
W
Reset:0 0 0 —————
Figure 7-5. Condition Code Register (CCR)