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MCF51QE128 MCU Series Reference Manual, Rev. 3
12 Freescale Semiconductor
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Section Number Title Page
6.7.11.1 KBI2 Interrupt Status and Control Register (KBI2SC) ................................142
6.7.11.2 KBI2 Interrupt Pin Select Register (KBI2PE) ..............................................142
6.7.11.3 KBI2 Interrupt Edge Select Register (KBI2ES) ...........................................143
Chapter 7
ColdFire Core
7.1 Introduction ...................................................................................................................................145
7.1.1 Overview .........................................................................................................................145
7.2 Memory Map/Register Description ...............................................................................................146
7.2.1 Data Registers (D0–D7) ..................................................................................................147
7.2.2 Address Registers (A0–A6) ............................................................................................148
7.2.3 Supervisor/User Stack Pointers (A7 and OTHER_A7) ..................................................148
7.2.4 Condition Code Register (CCR) .....................................................................................149
7.2.5 Program Counter (PC) ....................................................................................................150
7.2.6 Vector Base Register (VBR) ...........................................................................................150
7.2.7 CPU Configuration Register (CPUCR) ..........................................................................151
7.2.8 Status Register (SR) ........................................................................................................152
7.3 Functional Description ..................................................................................................................153
7.3.1 Instruction Set Architecture (ISA_C) .............................................................................153
7.3.2 Exception Processing Overview .....................................................................................154
7.3.2.1 Exception Stack Frame Definition ................................................................156
7.3.2.2 S08 and ColdFire Exception Processing Comparison ..................................157
7.3.3 Processor Exceptions ......................................................................................................159
7.3.3.1 Access Error Exception ................................................................................159
7.3.3.2 Address Error Exception ...............................................................................159
7.3.3.3 Illegal Instruction Exception .........................................................................160
7.3.3.4 Privilege Violation ........................................................................................161
7.3.3.5 Trace Exception ............................................................................................161
7.3.3.6 Unimplemented Line-A Opcode ...................................................................162
7.3.3.7 Unimplemented Line-F Opcode ...................................................................162
7.3.3.8 Debug Interrupt .............................................................................................162
7.3.3.9 RTE and Format Error Exception .................................................................162
7.3.3.10 TRAP Instruction Exception .........................................................................163
7.3.3.11 Unsupported Instruction Exception ..............................................................163
7.3.3.12 Interrupt Exception .......................................................................................163
7.3.3.13 Fault-on-Fault Halt .......................................................................................163
7.3.3.14 Reset Exception ............................................................................................164
7.3.4 Instruction Execution Timing .........................................................................................167
7.3.4.1 Timing Assumptions .....................................................................................167
7.3.4.2 MOVE Instruction Execution Times ............................................................168
7.3.4.3 Standard One Operand Instruction Execution Times ...................................169
7.3.4.4 Standard Two Operand Instruction Execution Times ...................................170