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Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG)
MCF51QE128 MCU Series Reference Manual, Rev. 3
368 Freescale Semiconductor
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WRITE_DREG Writes CSR2[31
–0] from the BDM interface. Classified as a non-intrusive BDM command.
WDEBUG Instruction Writes CSR2[23
–0] during the core’s execution of WDEBUG instruction. This instruction is
a privileged supervisor-mode instruction.
DRc: 0x02 (CSR2) Access: Supervisor read-only
BDM read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
PSTBP
0
000
0
BFHBR
0
0
PSTB
H
PSTBST 0 D1HRL
W BDFR
Power-on
Reset
000000 0 000000000
Other
Reset
00uuu0 u 000000000
1514131211109 876543210
R PSTBWA 0
APCD
IV16
0
PSTBRM PSTBSS
W
PSTBR
Reset Unaffected and Undefined 00000000
Figure 18-5. Configuration/Status Register 2 (CSR2)
Table 18-9. CSR2 Field Descriptions
Field Description
31
PSTBP
PST buffer stop. Signals if a PST buffer stop condition has been reached.
0 A PST trace buffer stop condition has not been reached
1 A PST trace buffer stop condition has been reached
30–26 Reserved, must be cleared.
25
BFHBR
BDM force halt on BDM reset. Determines operation of the device after a BDM reset. This bit is cleared after a
power-on reset and is unaffected by any other reset.
0 The device enters normal operation mode following a BDM reset.
1 The device enters in halt mode following a BDM reset, as if the BKGD pin was held low after a power-on-reset
or standard BDM-initiated reset.
24
BDFR
Background debug force reset. Forces a BDM reset to the device. This bit always reads as 0 after the reset has
been initiated.
0 No reset initiated.
1 Force a BDM reset.
20 Reserved, must be cleared.
23
PSTBH
PST trace buffer halt. Indicates if the processor is halted due to the PST trace buffer being full when recording in
a continuous mode.
0 PST trace buffer not full
1 CPU halted due to PST trace buffer being full in continuous mode
Table 18-8. CSR2 Reference Summary (continued)
Method Reference Details