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MCF51QE128 MCU Series Reference Manual, Rev. 3
Freescale Semiconductor 49
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Chapter 3 Modes of Operation
3.6 Run Modes
3.6.1 Run Mode
Run mode is the normal operating mode for the MCF51QE128/64/32. This mode is selected when the
BKGD/MS pin is high at the rising edge of the internal reset signal. Upon exiting reset, the CPU fetches
the supervisor SR and initial PC from locations 0x(00)00_0000 and 0x(00)00_0004 in the memory map
and executes code starting at the newly set value of the PC.
3.6.2 Low-Power Run Mode (LPrun)
In the low-power run mode, the on-chip voltage regulator is put into its standby (or loose regulation) state.
In this state, the power consumption is reduced to a minimum that allows CPU functionality. Power
consumption is reduced the most by disabling the clocks to all unused peripherals by clearing the
corresponding bits in the SCGC1 and SCGC2 registers
1
.
Before entering this mode, the following conditions must be met:
•FBELP
2
is the selected clock mode for the ICS. See Section 12.1.5.6, “FLL Bypassed External
Low Power (FBELP),” for more details.
• ICSC2[HGO] is cleared.
• The bus frequency is less than 125 kHz.
• The ADC must be in low-power mode (ADLPC=1) or disabled.
• Low-voltage detect must be disabled. The LVDE and/or LVDSE bit in SPMSC1 register must be
cleared.
• Flash programming/erasing is not allowed
After these conditions are met, low-power run mode can be entered by setting SPMSC2[LPR].
To re-enter standard run mode, clear the LPR bit. SPMSC2[LPRS] is a read-only status bit that can be used
to determine if the regulator is in full-regulation mode or not. When LPRS is cleared, the regulator is in
full-regulation mode and the MCU can run at full speed in any clock mode.
Assuming that SOPT1[BKGDPE] is set to enable BKGD/MS, the device also switches from LPrun to run
mode when it detects a negative transition on the BKGD/MS pin.
Low-power run mode also provides the option to return to full regulation if any interrupt occurs. This is
done by setting SPMSC2[LPWUI]. The ICS can then be set for full speed immediately in the interrupt
service routine.
3.6.2.1 BDM in Low-Power Run Mode
Low-power run mode cannot be entered when the MCU is in active background debug mode.
If a device is in low-power run mode, a falling edge on an active BKGD/MS pin exits low-power run mode,
clears the LPR and LPRS bits, and returns the device to normal run mode.
1. System clock gating control registers 1 and 2
2. FLL bypassed external low-power