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Timer/PWM Module (S08TPMV3)
MCF51QE128 MCU Series Reference Manual, Rev. 3
354 Freescale Semiconductor
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17.6.2.1.2 Center-Aligned PWM Case
When CPWMS is set, TOF is set when the timer counter changes direction from up-counting to
down-counting at the end of the terminal count (the value in the modulo register). In this case, TOF
corresponds to the end of a PWM period.
17.6.2.2 Channel Event Interrupt Description
The meaning of channel interrupts depends on the channel’s current mode (input-capture, output-compare,
edge-aligned PWM, or center-aligned PWM).
17.6.2.2.1 Input Capture Events
When a channel is configured as an input capture channel, the ELSnB and ELSnA control bits select no
edge (off), rising edges, falling edges, or any edge as the edge that triggers an input capture event. When
the selected edge is detected, the interrupt flag is set. The flag is cleared by the two-step sequence
described in Section 17.6.2, “Description of Interrupt Operation.”
17.6.2.2.2 Output Compare Events
When a channel is configured as an output compare channel, the interrupt flag is set each time the main
timer counter matches the 16-bit value in the channel value register. The flag is cleared by the two-step
sequence described Section 17.6.2, “Description of Interrupt Operation.”
17.6.2.2.3 PWM End-of-Duty-Cycle Events
There are two possibilities for channels configured for PWM operation. When the channel is configured
for edge-aligned PWM, the channel flag is set when the timer counter matches the channel value register
that marks the end of the active duty cycle period. When the channel is configured for center-aligned
PWM, the timer count matches the channel value register twice during each PWM cycle. In this CPWM
case, the channel flag is set at the start and at the end of the active duty cycle period, when the timer counter
matches the channel value register. The flag is cleared by the two-step sequence described Section 17.6.2,
“Description of Interrupt Operation.”