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MCF51QE128 MCU Series Reference Manual, Rev. 3
22 Freescale Semiconductor
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Section Number Title Page
18.4.1.5.8NOP ..........................................................................................397
18.4.1.5.9READ_CREG ..........................................................................397
18.4.1.5.10READ_DREG ........................................................................398
18.4.1.5.11READ_MEM.sz, READ_MEM.sz_WS ................................398
18.4.1.5.12READ_PSTB .........................................................................399
18.4.1.5.13READ_Rn ..............................................................................400
18.4.1.5.14READ_XCSR_BYTE ............................................................400
18.4.1.5.15READ_CSR2_BYTE .............................................................400
18.4.1.5.16READ_CSR3_BYTE .............................................................400
18.4.1.5.17SYNC_PC ..............................................................................401
18.4.1.5.18WRITE_CREG ......................................................................401
18.4.1.5.19WRITE_DREG ......................................................................402
18.4.1.5.20WRITE_MEM.sz, WRITE_MEM.sz_WS .............................402
18.4.1.5.21WRITE_Rn ............................................................................403
18.4.1.5.22WRITE_XCSR_BYTE ..........................................................404
18.4.1.5.23WRITE_CSR2_BYTE ...........................................................404
18.4.1.5.24WRITE_CSR3_BYTE ...........................................................404
18.4.1.6 Serial Interface Hardware Handshake Protocol ............................................404
18.4.1.7 Hardware Handshake Abort Procedure ........................................................406
18.4.2 Real-Time Debug Support ..............................................................................................409
18.4.3 Real-Time Trace Support ................................................................................................409
18.4.3.1 Begin Execution of Taken Branch (PST = 0x05) .........................................411
18.4.3.2 PST Trace Buffer (PSTB) .............................................................................413
18.4.3.3 PST/DDATA Example ..................................................................................413
18.4.3.4 Processor Status, Debug Data Definition ......................................................414
18.4.3.4.1User Instruction Set ..................................................................415
18.4.3.4.2Supervisor Instruction Set ........................................................418
18.4.4 Freescale-Recommended BDM Pinout ..........................................................................419
Appendix A
Revision History
A.1 Changes between Rev. 2 and Rev. 3 .............................................................................................421