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Timer/PWM Module (S08TPMV3)
MCF51QE128 MCU Series Reference Manual, Rev. 3
340 Freescale Semiconductor
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pin is forced low at the start of each new period (TPMxCNT=0x0000), and the pin is forced high when the
channel value register matches the timer counter.
Figure 17-3. High-True Pulse of an Edge-Aligned PWM
Figure 17-4. Low-True Pulse of an Edge-Aligned PWM
When the TPM is configured for center-aligned PWM and ELSnB:ELSnA are not cleared, the data
direction for all channels in this TPM are overridden, the TPMxCHn pins are forced to be outputs
controlled by the TPM, and the ELSnA bits control the polarity of each TPMxCHn output. If ELSnB is set
and ELSnA is cleared, the corresponding TPMxCHn pin is negated when the timer counter is counting up,
and the channel value register matches the timer counter. The TPMxCHn pin is asserted when the timer
counter is counting down, and the channel value register matches the timer counter. If ELSnA is set, the
corresponding TPMxCHn pin is asserted when the timer counter is counting up and the channel value
register matches the timer counter; the TPMxCHn pin is negated when the timer counter is counting down
and the channel value register matches the timer counter.
Figure 17-5. High-True Pulse of a Center-Aligned PWM
CHnF Bit
TOF Bit
0... 1 2 3 4 5 6 7 8 0 1 2 ...
TPMxMODH:TPMxMODL = 0x0008
TPMxMODH:TPMxMODL = 0x0005
TPMxCNTH:TPMxCNTL
TPMxCHn
CHnF Bit
TOF Bit
TPMxMODH:TPMxMODL = 0x0008
TPMxMODH:TPMxMODL = 0x0005
TPMxCNTH:TPMxCNTL
TPMxCHn
0... 12345678012...
CHnF Bit
TOF Bit
...
78
765
4
321 01234567876 5 ...
TPMxMODH:TPMxMODL = 0x0008
TPMxMODH:TPMxMODL = 0x0005
TPMxCNTH:TPMxCNTL
TPMxCHn