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MCF51QE128 MCU Series Reference Manual, Rev. 3
126 Freescale Semiconductor
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Chapter 6 Parallel Input/Output Control
6.7.3.7 Port C Slew Rate Enable Register (PTCSE)
6.7.3.8 Port C Drive Strength Selection Register (PTCDS)
6.7.4 Port D Registers
Port D is controlled by the registers listed below.
6.7.4.1 Port D Data Register (PTDD)
76543210
R
PTCSE7 PTCSE6 PTCSE5 PTCSE4 PTCSE3 PTCSE2 PTCSE1 PTCSE0
W
Reset:00000000
Figure 6-20. Slew Rate Enable for Port C Register (PTCSE)
Table 6-17. PTCSE Register Field Descriptions
Field Description
7–0
PTCSEn
Output Slew Rate Enable for Port C Bits. Each of these control bits determines if the output slew rate control is
enabled for the associated PTC pin. For port C pins configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port C bit n.
1 Output slew rate control enabled for port C bit n.
76543210
R
PTCDS7 PTCDS6 PTCDS5 PTCDS4 PTCDS3 PTCDS2 PTCDS1 PTCDS0
W
Reset:00000000
Figure 6-21. Drive Strength Selection for Port C Register (PTCDS)
Table 6-18. PTCDS Register Field Descriptions
Field Description
7–0
PTCDSn
Output Drive Strength Selection for Port C Bits. Each of these control bits selects between low and high output
drive for the associated PTC pin. For port C pins configured as inputs, these bits have no effect.
0 Low output drive strength selected for port C bit n.
1 High output drive strength selected for port C bit n.
76543210
R
PTDD7 PTDD6 PTDD5 PTDD4 PTDD3 PTDD2 PTDD1 PTDD0
W
Reset:00000000
Figure 6-22. Port D Data Register (PTDD)