Freescale Semiconductor MCF51QE128RM Answering Machine User Manual


 
Internal Clock Source (S08ICSV3)
MCF51QE128 MCU Series Reference Manual, Rev. 3
Freescale Semiconductor 247
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12.1.3 Features
Key features of the ICS module are:
Frequency-locked loop (FLL) is trimmable for accuracy
Internal or external reference clocks can be used to control the FLL
Reference divider is provided for external clock
Internal reference clock has 9 trim bits available
Internal or external reference clocks can be selected as the clock source for the MCU
Whichever clock is selected as the source can be divided down
2 bit select for clock divider is provided
Allowable dividers are: 1, 2, 4, 8
Control signals for a low power oscillator as the external reference clock are provided
HGO, RANGE, EREFS, ERCLKEN, EREFSTEN
FLL Engaged Internal mode is automatically selected out of reset
BDC clock is provided as a constant divide by 2 of the low range DCO output
Three selectable digitally controlled oscillators (DCO) optimized for different frequency ranges.
Option to maximize output frequency for a 32768 Hz external reference clock source.