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MCF51QE128 MCU Series Reference Manual, Rev. 3
10 Freescale Semiconductor
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Section Number Title Page
Chapter 6
Parallel Input/Output Control
6.1 Port Data and Data Direction ........................................................................................................113
6.2 Pull-up, Slew Rate, and Drive Strength ........................................................................................114
6.2.1 Port Internal Pull-up Enable ...........................................................................................114
6.2.2 Port Slew Rate Enable ....................................................................................................114
6.2.3 Port Drive Strength Select ..............................................................................................115
6.3 Port Data Set, Clear and Toggle Data Registers ............................................................................115
6.3.1 Port Data Set Registers ...................................................................................................116
6.3.2 Port Data Clear Registers ................................................................................................116
6.3.3 Port Data Toggle Register ...............................................................................................116
6.4 V1 ColdFire Rapid GPIO Functionality ........................................................................................116
6.5 Keyboard Interrupts .......................................................................................................................116
6.5.1 Edge Only Sensitivity .....................................................................................................117
6.5.2 Edge and Level Sensitivity .............................................................................................117
6.5.3 Pull-up/Pull-down Resistors ...........................................................................................117
6.5.4 Keyboard Interrupt Initialization ....................................................................................118
6.6 Pin Behavior in Stop Modes ..........................................................................................................118
6.7 Parallel I/O, Keyboard Interrupt, and Pin Control Registers ........................................................118
6.7.1 Port A Registers ..............................................................................................................118
6.7.1.1 Port A Data Register (PTAD) .......................................................................119
6.7.1.2 Port A Data Direction Register (PTADD) ....................................................119
6.7.1.3 Port A Pull Enable Register (PTAPE) ...........................................................119
6.7.1.4 Port A Slew Rate Enable Register (PTASE) .................................................120
6.7.1.5 Port A Drive Strength Selection Register (PTADS) .....................................120
6.7.2 Port B Registers ..............................................................................................................121
6.7.2.1 Port B Data Register (PTBD) ........................................................................121
6.7.2.2 Port B Data Direction Register (PTBDD) .....................................................121
6.7.2.3 Port B Pull Enable Register (PTBPE) ...........................................................122
6.7.2.4 Port B Slew Rate Enable Register (PTBSE) .................................................122
6.7.2.5 Port B Drive Strength Selection Register (PTBDS) .....................................123
6.7.3 Port C Registers ..............................................................................................................123
6.7.3.1 Port C Data Register (PTCD) ........................................................................123
6.7.3.2 Port C Data Direction Register (PTCDD) .....................................................124
6.7.3.3 Port C Data Set Register (PTCSET) .............................................................124
6.7.3.4 Port C Data Clear Register (PTCCLR) .........................................................124
6.7.3.5 Port C Toggle Register (PTCTOG) ...............................................................125
6.7.3.6 Port C Pull Enable Register (PTCPE) ...........................................................125
6.7.3.7 Port C Slew Rate Enable Register (PTCSE) .................................................126
6.7.3.8 Port C Drive Strength Selection Register (PTCDS) .....................................126
6.7.4 Port D Registers ..............................................................................................................126
6.7.4.1 Port D Data Register (PTDD) .......................................................................126