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MCF51QE128 MCU Series Reference Manual, Rev. 3
140 Freescale Semiconductor
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Chapter 6 Parallel Input/Output Control
6.7.10 Keyboard Interrupt 1 (KBI1) Registers
KBI1 is controlled by the registers listed below. Table 6-52 shows KBI1 pin mapping to the port I/O pins.
6.7.10.1 KBI1 Interrupt Status and Control Register (KBI1SC)
Table 6-51. PTJDS Register Field Descriptions
Field Description
7–0
PTJDSn
Output Drive Strength Selection for Port J Bits. Each of these control bits selects between low and high output
drive for the associated PTJ pin. For port J pins configured as inputs, these bits have no effect.
0 Low output drive strength selected for port J bit n.
1 High output drive strength selected for port J bit n.
Table 6-52. KBI1 Pin Mapping
Port pin PTB3 PTB2 PTB1 PTB0 PTA3 PTA2 PTA1 PTA0
KBI1 pin KBI1P7 KBI1P6 KBI1P5 KBI1P4 KBI1P3 KBI1P2 KBI1P1 KBI1P0
76543210
R0000KBF0
KBIE KBIMOD
W KBACK
Reset:00000000
Figure 6-55. KBI1 Interrupt Status and Control Register (KBI1SC)
Table 6-53. KBI1SC Register Field Descriptions
Field Description
7–4 Reserved, should be cleared.
3
KBF
KBI1 Interrupt Flag. KBF indicates when a KBI1 interrupt is detected. Writes have no effect on KBF.
0 No KBI1 interrupt detected.
1 KBI1 interrupt detected.
2
KBACK
KBI1 Interrupt Acknowledge. Writing a 1 to KBACK is part of the flag clearing mechanism. KBACK always reads
as 0.
1
KBIE
KBI1 Interrupt Enable. KBIE determines whether a KBI1 interrupt is requested.
0 KBI1 interrupt request not enabled.
1 KBI1 interrupt request enabled.
0
KBIMOD
KBI1 Detection Mode. KBIMOD (along with the KBI1ES bits) controls the detection mode of the KBI1 interrupt
pins.
0 KBI1 pins detect edges only.
1 KBI1 pins detect edges and levels.