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ColdFire Core
MCF51QE128 MCU Series Reference Manual, Rev. 3
Freescale Semiconductor 147
• 16-bit status register (SR)
• 32-bit supervisor stack pointer (SSP)
• 32-bit vector base register (VBR)
• 32-bit CPU configuration register (CPUCR)
7.2.1 Data Registers (D0–D7)
D0–D7 data registers are for bit (1-bit), byte (8-bit), word (16-bit) and longword (32-bit) operations; they
can also be used as index registers.
Table 7-1. ColdFire Core Programming Model
BDM Command
1
Register
Width
(bits)
Access Reset Value
Written with
MOVEC
2
Section/Page
Supervisor/User Access Registers
Load: 0x60
Store: 0x40
Data Register 0 (D0) 32 R/W 0xCF10_0029 No 7.2.1/7-147
Load: 0x61
Store: 0x41
Data Register 1 (D1) 32 R/W 0x1090_0050 No 7.2.1/7-147
Load: 0x62–7
Store: 0x42–7
Data Register 2–7 (D2–D7) 32 R/W POR: Undefined
Else: Unaffected
No 7.2.1/7-147
Load: 0x68–8E
Store: 0x48–8E
Address Register 0–6 (A0–A6) 32 R/W POR: Undefined
Else: Unaffected
No 7.2.2/7-148
Load: 0x6F
Store: 0x4F
User A7 Stack Pointer (A7) 32 R/W POR: Undefined
Else: Unaffected
No 7.2.3/7-148
Load: 0xEE
Store: 0xCE
Condition Code Register (CCR) 8 R/W POR: Undefined
Else: Unaffected
No 7.2.4/7-149
Load: 0xEF
Store: 0xCF
Program Counter (PC) 32 R/W Contents of
location
0x0000_0004
No 7.2.5/7-150
Supervisor Access Only Registers
Load: 0xE0
Store: 0xC0
Supervisor A7 Stack Pointer
(OTHER_A7)
32 R/W Contents of
location
0x0000_0000
No 7.2.3/7-148
Load: 0xE1
Store: 0xC1
Vector Base Register (VBR) 32 R/W 0x0000_0000 Yes;
Rc = 0x801
7.2.6/7-150
Load: 0xE2
Store: 0xC2
CPU Configuration Register (CPUCR) 32 W 0x0000_0000 Yes;
Rc = 0x802
7.2.7/7-151
Load: 0xEE
Store: 0xCE
Status Register (SR) 16 R/W 0x27-- No 7.2.8/7-152
1
The values listed in this column represent the 8-bit BDM command code used when accessing the core registers via the 1-pin
BDM port. For more information see .” (These BDM commands are not similar to other ColdFire processors.)
2
If the given register is written using the MOVEC instruction, the 12-bit control register address (Rc) is also specified.