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MCF51QE128 MCU Series Reference Manual, Rev. 3
Freescale Semiconductor 325
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16.4.5 SPI Data Register (SPIxD)
Reads of this register returns the data read from the receive data buffer. Writes to this register write data
to the transmit data buffer. When the SPI is configured as a master, writing data to the transmit data buffer
initiates an SPI transfer.
Data should not be written to the transmit data buffer unless SPIxS[SPTEF] is set, indicating there is room
in the transmit buffer to queue a new transmit byte.
Data may be read from SPIxD any time after SPRF is set and before another transfer is finished. Failure
to read the data out of the receive data buffer before a new transfer ends causes a receive overrun condition
and the data from the new transfer is lost.
16.5 Functional Description
An SPI transfer is initiated by checking for the SPI transmit buffer empty flag (SPIxS[SPTEF] = 1) and
then writing a byte of data to the SPI data register (SPIxD) in the master SPI device. When the SPI shift
register is available, this byte of data is moved from the transmit data buffer to the shifter, SPTEF is set to
5
SPTEF
SPI Transmit Buffer Empty Flag. This bit is set when there is room in the transmit data buffer. It is cleared by
reading SPIxS with SPTEF set, followed by writing a data value to the transmit buffer at SPIxD. SPIxS must be
read with SPTEF set before writing data to SPIxD or the SPIxD write is ignored. SPTEF generates a CPU
interrupt request if SPIxC1[SPTIE] is also set. SPTEF is automatically set when a data byte transfers from the
transmit buffer into the transmit shift register. For an idle SPI (no data in the transmit buffer or the shift register
and no transfer in progress), data written to SPIxD is transferred to the shifter almost immediately so SPTEF is
set within two bus cycles allowing a second 8-bit data value to be queued into the transmit buffer. After completion
of the transfer of the value in the shift register, the queued value from the transmit buffer is automatically moved
to the shifter and SPTEF is set, indicating there is room for new data in the transmit buffer. If no new data is
waiting in the transmit buffer, SPTEF remains set and no data moves from the buffer to the shifter.
0 SPI transmit buffer not empty
1 SPI transmit buffer empty
4
MODF
Master Mode Fault Flag. MODF is set if the SPI is configured as a master and the slave select input asserts,
indicating some other SPI device is also configured as a master. The SS pin acts as a mode fault error input only
when MSTR and MODFEN are set and SSOE is cleared. Otherwise, MODF is never set. MODF is cleared by
reading MODF while it is 1, then writing to the SPIxC1 register.
0 No mode fault error
1 Mode fault error detected
3–0 Reserved, should be cleared.
76543210
R
Data
W
Reset00000000
Figure 16-9. SPI Data Register (SPIxD)
Table 16-5. SPIxS Register Field Descriptions
Field Description