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MCF51QE128 MCU Series Reference Manual, Rev. 3
Freescale Semiconductor 321
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output enable bit determines whether this pin acts as the mode fault input (SPIxC1[SSOE] = 0) or as the
slave select output (SSOE = 1).
16.3 Modes of Operation
16.3.1 SPI in Stop Modes
The SPI is disabled in all stop modes, regardless of the settings before executing the STOP instruction.
During stop2 mode, the SPI module is fully powered down. Upon wake-up from stop2 mode, the SPI
module is in the reset state. During stop3 mode, clocks to the SPI module are halted. No registers are
affected. If stop3 is exited with a reset, the SPI is placed into its reset state. If stop3 is exited with an
interrupt, the SPI continues from the state it was in when stop3 was entered.
16.4 Register Definition
The SPI contains five 8-bit registers to select SPI options, control baud rate, report SPI status, and for
transmit/receive data.
Refer to the direct-page register summary in the memory chapter of this document for the absolute address
assignments for all SPI registers. This section refers to registers and control bits only by their names, and
a Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
16.4.1 SPI Control Register 1 (SPIxC1)
This read/write register includes the SPI enable control, interrupt enables, and configuration options.
76543210
R
SPIE SPE SPTIE MSTR CPOL CPHA SSOE LSBFE
W
Reset00000100
Figure 16-5. SPI Control Register 1 (SPIxC1)
Table 16-1. SPIxC1 Field Descriptions
Field Description
7
SPIE
SPI Interrupt Enable (for SPRF and MODF). This is the interrupt enable for SPI receive buffer full (SPRF) and
mode fault (MODF) events.
0 Interrupts from SPRF and MODF inhibited (use polling)
1 When SPRF or MODF is 1, request a hardware interrupt
6
SPE
SPI System Enable. Disabling the SPI halts any transfer in progress, clears data buffers, and initializes internal
state machines. SPRF is cleared and SPTEF is set to indicate the SPI transmit data buffer is empty.
0 SPI system inactive
1 SPI system enabled