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Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG)
MCF51QE128 MCU Series Reference Manual, Rev. 3
Freescale Semiconductor 393
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2. Delays 16 cycles to allow the host to stop driving the high speed-up pulse.
3. Drives BKGD low for 128 BDC clock cycles.
4. Drives a 1-cycle high speed-up pulse to force a fast rise time on BKGD.
5. Removes all drive to the BKGD pin so it reverts to high impedance.
The host measures the low time of this 128-cycle sync response pulse and determines the correct speed for
subsequent BDC communications. Typically, the host can determine the correct communication speed
within a few percent of the actual target speed and the serial protocol can easily tolerate this speed error.
18.4.1.5.2 ACK_DISABLE
Disables the serial communication handshake protocol. The subsequent commands, issued after the
ACK_DISABLE command, do not execute the hardware handshake protocol. This command is not
followed by an ACK pulse.
18.4.1.5.3 ACK_ENABLE
Enables the hardware handshake protocol in the serial communication. The hardware handshake is
implemented by an acknowledge (ACK) pulse issued by the target MCU in response to a host command.
The ACK_ENABLE command is interpreted and executed in the BDC logic without the need to interface
with the CPU. However, an acknowledge (ACK) pulse is issued by the target device after this command
is executed. This feature can be used by the host in order to evaluate if the target supports the hardware
handshake protocol. If the target supports the hardware handshake protocol, subsequent commands are
enabled to execute the hardware handshake protocol, otherwise this command is ignored by the target.
For additional information about the hardware handshake protocol, refer to Section 18.4.1.6, “Serial
Interface Hardware Handshake Protocol,” and Section 18.4.1.7, “Hardware Handshake Abort Procedure.”
Disable host/target handshake protocol Always Available
0x03
host →
target
D
L
Y
Enable host/target handshake protocol Always Available
0x02
host →
target
D
L
Y