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MCF51QE128 MCU Series Reference Manual, Rev. 3
Freescale Semiconductor 21
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Section Number Title Page
17.6.2 Description of Interrupt Operation .................................................................................353
17.6.2.1 Timer Overflow Interrupt (TOF) Description ...............................................353
17.6.2.1.1Normal Case .............................................................................353
17.6.2.1.2Center-Aligned PWM Case ......................................................354
17.6.2.2 Channel Event Interrupt Description ............................................................354
17.6.2.2.1Input Capture Events ................................................................354
17.6.2.2.2Output Compare Events ...........................................................354
17.6.2.2.3PWM End-of-Duty-Cycle Events ............................................354
Chapter 18
Version 1 ColdFire Debug (CF1_DEBUG)
18.1 Introduction ...................................................................................................................................355
18.1.1 Overview .........................................................................................................................356
18.1.2 Features ...........................................................................................................................357
18.1.3 Modes of Operations .......................................................................................................357
18.2 External Signal Descriptions .........................................................................................................359
18.3 Memory Map/Register Definition .................................................................................................360
18.3.1 Configuration/Status Register (CSR) ..............................................................................361
18.3.2 Extended Configuration/Status Register (XCSR) ...........................................................364
18.3.3 Configuration/Status Register 2 (CSR2) .........................................................................367
18.3.4 Configuration/Status Register 3 (CSR3) .........................................................................370
18.3.5 BDM Address Attribute Register (BAAR) .....................................................................371
18.3.6 Address Attribute Trigger Register (AATR) ...................................................................372
18.3.7 Trigger Definition Register (TDR) .................................................................................373
18.3.8 Program Counter Breakpoint/Mask Registers (PBR0–3, PBMR) ..................................376
18.3.9 Address Breakpoint Registers (ABLR, ABHR) .............................................................378
18.3.10Data Breakpoint and Mask Registers (DBR, DBMR) ....................................................379
18.3.11Resulting Set of Possible Trigger Combinations ............................................................380
18.4 Functional Description ..................................................................................................................380
18.4.1 Background Debug Mode (BDM) ..................................................................................380
18.4.1.1 CPU Halt .......................................................................................................381
18.4.1.2 Background Debug Serial Interface Controller (BDC) ................................383
18.4.1.3 BDM Communication Details ......................................................................384
18.4.1.4 BDM Command Set Descriptions ................................................................387
18.4.1.5 BDM Command Set Summary .....................................................................390
18.4.1.5.1SYNC .......................................................................................392
18.4.1.5.2ACK_DISABLE ......................................................................393
18.4.1.5.3ACK_ENABLE .......................................................................393
18.4.1.5.4BACKGROUND .....................................................................394
18.4.1.5.5DUMP_MEM.sz, DUMP_MEM.sz_WS .................................394
18.4.1.5.6FILL_MEM.sz, FILL_MEM.sz_WS .......................................395
18.4.1.5.7GO ............................................................................................397