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Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG)
MCF51QE128 MCU Series Reference Manual, Rev. 3
Freescale Semiconductor 377
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Figure 18-12 shows PBMR. PBMR is accessible in supervisor mode using the WDEBUG instruction and
via the BDM port using the WRITE_DREG command. PBMR only masks PBR0.
DRc: 0x08 (PBR0) Access: Supervisor write-only
BDM write-only
313029282726252423222120191817161514131211109876543210
R
WAddress
Reset––––––––––––––––––––––––––––––––
Figure 18-10. Program Counter Breakpoint Register 0 (PBR0)
Table 18-15. PBR0 Field Descriptions
Field Description
31–0
Address
PC breakpoint address. The address to be compared with the PC as a breakpoint trigger. Since all instruction sizes
are multiples of 2 bytes, bit 0 of the address should always be zero.
DRc: 0x18 (PBR1)
0x1A (PBR2)
0x1C (PBR3)
Access: Supervisor write-only
BDM write-only
313029282726252423222120191817161514131211109876543210
R
W Address V
Reset–––––––––––––––––––––––––––––––0
Figure 18-11. Program Counter Breakpoint Register n (PBRn, n = 1,2,3)
Table 18-16. PBRn Field Descriptions
Field Description
31–1
Address
PC breakpoint address. The 31-bit address to be compared with the PC as a breakpoint trigger.
0
V
Valid bit. This bit must be set for the PC breakpoint to occur at the address specified in the Address field.
0 PBR is disabled.
1 PBR is enabled.
DRc: 0x09 (PBMR) Access: Supervisor write-only
BDM write-only
313029282726252423222120191817161514131211109876543210
R
WMask
Reset––––––––––––––––––––––––––––––––
Figure 18-12. Program Counter Breakpoint Mask Register (PBMR)