Freescale Semiconductor MCF51QE128RM Answering Machine User Manual


 
MCF51QE128 MCU Series Reference Manual, Rev. 3
Freescale Semiconductor 87
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NOTE
The BDM can also perform a mass erase and verify command. See
Chapter 18, “Version 1 ColdFire Debug (CF1_DEBUG),” for details.
4.5.3 Illegal Flash Operations
4.5.3.1 Flash Access Violations
The FACCERR flag is set during the command write sequence if any of the following illegal steps are
performed, causing the command write sequence to immediately abort:
1. Writing to a flash address before initializing the FCDIV register.
2. Writing a byte, word, or misaligned longword to a valid flash address.
3. Writing to any flash register other than FCMD after writing to a flash address.
4. Writing to a second flash address in the same command write sequence.
5. Writing an invalid command to the FCMD register unless the address written was in a protected
area of the flash array.
6. Writing a command other than burst program while FCBEF is set and FCCF is clear.
7. When security is enabled, writing a command other than erase verify or mass erase to the FCMD
register when the write originates from a non-secure memory location or from the background
debug mode.
8. Writing to a flash address after writing to the FCMD register.
9. Writing to any flash register other than FSTAT (to clear FCBEF) after writing to the FCMD
register.
10. Writing a 0 to the FCBEF flag in the FSTAT register to abort a command write sequence.
The FACCERR flag is also set if the MCU enters stop mode while any command is active (FCCF=0). The
operation is aborted immediately and, if burst programming, any pending burst program command is
purged (see Section 4.5.4.2, “Stop Modes”).
The FACCERR flag does not set if any flash register is read during a valid command write sequence.
If the flash memory is read during execution of an algorithm (FCCF = 0), the read operation returns invalid
data and the FACCERR flag is not set.
If the FACCERR flag is set in the FSTAT register, clear the FACCERR flag before starting another
command write sequence (see Section 4.4.2.5, “Flash Status Register (FSTAT)”).