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MCF51QE128 MCU Series Reference Manual, Rev. 3
Freescale Semiconductor 9
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Section Number Title Page
4.5.4.1 Wait Mode .......................................................................................................88
4.5.4.2 Stop Modes .....................................................................................................88
4.5.4.3 Background Debug Mode ...............................................................................88
4.5.5 Security .............................................................................................................................89
4.5.5.1 Unsecuring the MCU using Backdoor Key Access ........................................89
4.5.6 Resets ................................................................................................................................90
4.5.6.1 Flash Reset Sequence ......................................................................................90
4.5.6.2 Reset While Flash Command Active ..............................................................90
4.5.6.3 Program and Erase Times ...............................................................................90
4.6 Security ............................................................................................................................................91
Chapter 5
Resets, Interrupts, and General System Control
5.1 Introduction .....................................................................................................................................93
5.2 Features ...........................................................................................................................................93
5.3 Microcontroller Reset ......................................................................................................................93
5.3.1 Computer Operating Properly (COP) Watchdog ..............................................................94
5.3.2 Illegal Operation Reset .....................................................................................................95
5.3.3 Illegal Address Reset ........................................................................................................95
5.4 Interrupts and Exceptions ................................................................................................................95
5.4.1 External Interrupt Request (IRQ) Pin ...............................................................................95
5.4.1.1 Pin Configuration Options ..............................................................................95
5.4.1.2 Edge and Level Sensitivity .............................................................................96
5.4.1.3 External Interrupt Initialization ......................................................................96
5.5 Low-Voltage Detect (LVD) System ................................................................................................96
5.5.1 Power-On Reset Operation ...............................................................................................96
5.5.2 LVD Reset Operation ........................................................................................................97
5.5.3 LVD Interrupt Operation ...................................................................................................97
5.5.4 Low-Voltage Warning (LVW) Interrupt Operation ...........................................................97
5.6 Peripheral Clock Gating ..................................................................................................................97
5.7 Reset, Interrupt, and System Control Registers and Control Bits ...................................................97
5.7.1 Interrupt Pin Request Status and Control Register (IRQSC) ............................................98
5.7.2 System Reset Status Register (SRS) .................................................................................99
5.7.3 System Options Register 1 (SOPT1) ..............................................................................100
5.7.4 System Options Register 2 (SOPT2) ..............................................................................101
5.7.5 System Device Identification Register (SDIDH, SDIDL) ..............................................102
5.7.6 System Power Management Status and Control 1 Register (SPMSC1) .........................103
5.7.7 System Power Management Status and Control 2 Register (SPMSC2) .........................104
5.7.8 System Power Management Status and Control 3 Register (SPMSC3) .........................105
5.7.9 System Clock Gating Control 1 Register (SCGC1) ........................................................107
5.7.10 System Clock Gating Control 2 Register (SCGC2) ........................................................107