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MCF51QE128 MCU Series Reference Manual, Rev. 3
Freescale Semiconductor 135
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Chapter 6 Parallel Input/Output Control
6.7.7.3 Port G Pull Enable Register (PTGPE)
The port G pull enable register enables pull-ups on the corresponding PTG pin. In some cases, a pull-down
device is enabled if pull-downs are supported by an alternate pin function (e.g., KBI).
6.7.7.4 Port G Slew Rate Enable Register (PTGSE)
6.7.7.5 Port G Drive Strength Selection Register (PTGDS)
76543210
R
PTGPE7 PTGPE6 PTGPE5 PTGPE4 PTGPE3 PTGPE2 PTGPE1 PTGPE0
W
Reset:00000000
Figure 6-42. Internal Pull Enable for Port G Register (PTGPE)
Table 6-39. PTGPE Register Field Descriptions
Field Description
7–0
PTGPEn
Internal Pull Enable for Port G Bits. Each of these control bits determines if the internal pull-up device is enabled
for the associated PTG pin. For port G pins configured as outputs, these bits have no effect and the internal pull
devices are disabled.
0 Internal pull-up device disabled for port G bit n.
1 Internal pull-up device enabled for port G bit n.
76543210
R
PTGSE7 PTGSE6 PTGSE5 PTGSE4 PTGSE3 PTGSE2 PTGSE1 PTGSE0
W
Reset:00000000
Figure 6-43. Slew Rate Enable for Port G Register (PTGSE)
Table 6-40. PTGSE Register Field Descriptions
Field Description
7–0
PTGSEn
Output Slew Rate Enable for Port G Bits. Each of these control bits determines if the output slew rate control is
enabled for the associated PTG pin. For port G pins configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port G bit n.
1 Output slew rate control enabled for port G bit n.
76543210
R
PTGDS7 PTGDS6 PTGDS5 PTGDS4 PTGDS3 PTGDS2 PTGDS1 PTGDS0
W
Reset:00000000
Figure 6-44. Drive Strength Selection for Port G Register (PTGDS)