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Chapter 18 Version 1 ColdFire Debug (CF1_DEBUG)
MCF51QE128 MCU Series Reference Manual, Rev. 3
404 Freescale Semiconductor
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18.4.1.5.22 WRITE_XCSR_BYTE
Write the special status byte of XCSR (XCSR[31–24]). This command can be executed in any mode.
18.4.1.5.23 WRITE_CSR2_BYTE
Write the most significant byte of CSR2 (CSR2[31–24]). This command can be executed in any mode.
18.4.1.5.24 WRITE_CSR3_BYTE
Write the most significant byte of CSR3 (CSR3[31
–24]). This command can be executed in any mode.
18.4.1.6 Serial Interface Hardware Handshake Protocol
BDC commands that require CPU execution are ultimately treated at the core clock rate. Since the BDC
clock source can be asynchronous relative to the bus frequency when CLKSW is cleared, it is necessary
to provide a handshake protocol so the host can determine when an issued command is executed by the
CPU. This section describes this protocol.
The hardware handshake protocol signals to the host controller when an issued command was successfully
executed by the target. This protocol is implemented by a low pulse (16 BDC clock cycles) followed by a
brief speedup pulse on the BKGD pin, generated by the target MCU when a command, issued by the host,
has been successfully executed. See Figure 18-19. This pulse is referred to as the ACK pulse. After the
ACK pulse is finished, the host can start the data-read portion of the command if the last-issued command
was a read command, or start a new command if the last command was a write command or a control
command (BACKGROUND, GO, NOP, SYNC_PC). The ACK pulse is not issued earlier than 32 BDC
Write XCSR Status Byte Always Available
0x0D
XCSR Data
[31–24]
host →
target
host →
target
Write CSR2 Status Byte Always Available
0x0E
CSR2 Data
[31–24]
host →
target
host →
target
Write CSR3 Status Byte Always Available
0x0F
CSR3 Data
[31–24]
host →
target
host →
target