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MCF51QE128 MCU Series Reference Manual, Rev. 3
120 Freescale Semiconductor
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Chapter 6 Parallel Input/Output Control
6.7.1.4 Port A Slew Rate Enable Register (PTASE)
6.7.1.5 Port A Drive Strength Selection Register (PTADS)
76543210
R
PTAPE7 PTAPE6 PTAPE5 PTAPE4
1
PTAPE3 PTAPE2 PTAPE1 PTAPE0
W
Reset:00000000
1
PTAPE4 has no effect on the output-only PTA4 pin.
Figure 6-6. Internal Pull Enable for Port A Register (PTAPE)
Table 6-3. PTAPE Register Field Descriptions
Field Description
7–0
PTAPEn
Internal Pull Enable for Port A Bits. Each of these control bits determines if the internal pull-up or pull-down device
is enabled for the associated PTA pin. For port A pins configured as outputs, these bits have no effect and the
internal pull devices are disabled.
0 Internal pull-up/pull-down device disabled for port A bit n.
1 Internal pull-up/pull-down device enabled for port A bit n.
76543210
R
PTASE7 PTASE6 PTASE5
1
PTASE4 PTASE3 PTASE2 PTASE1 PTASE0
W
Reset:00000000
1
PTASE5 has no effect on the open drain PTA5 pin.
Figure 6-7. Slew Rate Enable for Port A Register (PTASE)
Table 6-4. PTASE Register Field Descriptions
Field Description
7–0
PTASEn
Output Slew Rate Enable for Port A Bits. Each of these control bits determines if the output slew rate control is
enabled for the associated PTA pin. For port A pins configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
76543210
R
PTADS7 PTADS6 PTADS5
1
PTADS4 PTADS3 PTADS2 PTADS1 PTADS0
W
Reset:00000000
1
PTADS5 has no effect on the open drain PTA5 pin.
Figure 6-8. Drive Strength Selection for Port A Register (PTADS)