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MCF51QE128 MCU Series Reference Manual, Rev. 3
Freescale Semiconductor 133
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Chapter 6 Parallel Input/Output Control
6.7.6.4 Port F Slew Rate Enable Register (PTFSE)
6.7.6.5 Port F Drive Strength Selection Register (PTFDS)
76543210
R
PTFPE7 PTFPE6 PTFPE5 PTFPE4 PTFPE3 PTFPE2 PTFPE1 PTFPE0
W
Reset:00000000
Figure 6-37. Internal Pull Enable for Port F Register (PTFPE)
Table 6-34. PTFPE Register Field Descriptions
Field Description
7–0
PTFPEn
Internal Pull Enable for Port F Bits. Each of these control bits determines if the internal pull-up device is enabled
for the associated PTF pin. For port F pins configured as outputs, these bits have no effect and the internal pull
devices are disabled.
0 Internal pull-up device disabled for port F bit n.
1 Internal pull-up device enabled for port F bit n.
76543210
R
PTFSE7 PTFSE6 PTFSE5 PTFSE4 PTFSE3 PTFSE2 PTFSE1 PTFSE0
W
Reset:00000000
Figure 6-38. Slew Rate Enable for Port F Register (PTFSE)
Table 6-35. PTFSE Register Field Descriptions
Field Description
7–0
PTFSEn
Output Slew Rate Enable for Port F Bits. Each of these control bits determines if the output slew rate control is
enabled for the associated PTF pin. For port F pins configured as inputs, these bits have no effect.
0 Output slew rate control disabled for port F bit n.
1 Output slew rate control enabled for port F bit n.
76543210
R
PTFDS7 PTFDS6 PTFDS5 PTFDS4 PTFDS3 PTFDS2 PTFDS1 PTFDS0
W
Reset:00000000
Figure 6-39. Drive Strength Selection for Port F Register (PTFDS)