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MCF51QE128 MCU Series Reference Manual, Rev. 3
16 Freescale Semiconductor
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Section Number Title Page
11.6.1.3 Analog Input Pins .........................................................................................237
11.6.2 Sources of Error ..............................................................................................................238
11.6.2.1 Sampling Error ..............................................................................................238
11.6.2.2 Pin Leakage Error .........................................................................................238
11.6.2.3 Noise-Induced Errors ....................................................................................238
11.6.2.4 Code Width and Quantization Error .............................................................239
11.6.2.5 Linearity Errors .............................................................................................239
11.6.2.6 Code Jitter, Non-Monotonicity, and Missing Codes .....................................240
Chapter 12
Internal Clock Source (S08ICSV3)
12.1 Introduction ...................................................................................................................................243
12.1.1 External Oscillator ..........................................................................................................243
12.1.2 Stop2 Mode Considerations ............................................................................................243
12.1.3 Features ...........................................................................................................................247
12.1.4 Block Diagram ................................................................................................................248
12.1.5 Modes of Operation ........................................................................................................248
12.1.5.1 FLL Engaged Internal (FEI) .........................................................................248
12.1.5.2 FLL Engaged External (FEE) .......................................................................248
12.1.5.3 FLL Bypassed Internal (FBI) ........................................................................248
12.1.5.4 FLL Bypassed Internal Low Power (FBILP) ...............................................249
12.1.5.5 FLL Bypassed External (FBE) .....................................................................249
12.1.5.6 FLL Bypassed External Low Power (FBELP) .............................................249
12.1.5.7 Stop (STOP) ..................................................................................................249
12.2 External Signal Description ..........................................................................................................249
12.3 Register Definition ........................................................................................................................249
12.3.1 ICS Control Register 1 (ICSC1) .....................................................................................250
12.3.2 ICS Control Register 2 (ICSC2) .....................................................................................251
12.3.3 ICS Trim Register (ICSTRM) .........................................................................................251
12.3.4 ICS Status and Control (ICSSC) .....................................................................................252
12.4 Functional Description ..................................................................................................................254
12.4.1 Operational Modes ..........................................................................................................254
12.4.1.1 FLL Engaged Internal (FEI) .........................................................................254
12.4.1.2 FLL Engaged External (FEE) .......................................................................255
12.4.1.3 FLL Bypassed Internal (FBI) ........................................................................255
12.4.1.4 FLL Bypassed Internal Low Power (FBILP) ...............................................255
12.4.1.5 FLL Bypassed External (FBE) .....................................................................255
12.4.1.6 FLL Bypassed External Low Power (FBELP) .............................................256
12.4.1.7 Stop ...............................................................................................................256
12.4.2 Mode Switching ..............................................................................................................256
12.4.3 Bus Frequency Divider ...................................................................................................256
12.4.4 Low Power Bit Usage .....................................................................................................257