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MCF51QE128 MCU Series Reference Manual, Rev. 3
Freescale Semiconductor 331
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Chapter 17
Timer/Pulse-Width Modulator (S08TPMV3)
17.1 Introduction
Figure 17-1 shows the MCF51QE128 Series block diagram with the TPM highlighted.
17.1.1 ACMP/TPM Configuration Information
The ACMP modules can be configured to connect the output of the analog comparator to a TPM input
capture channel 0 by setting the corresponding SOPT2[ACICx] bit. With ACICx set, the TPMxCH0 pin is
not available externally regardless of the configuration of the TPMx module.
The ACMP1 output can be connected to TPM1CH0; The ACMP2 output can be connected to TPM2CH0.
17.1.2 TPM Clock Gating
The bus clock to TPM1, TPM2, and TPM3 can be gated on and off using the SCGC1[TPMx] bits. These
bits are set after any reset, which enables the bus clock to this module. To conserve power, these bits can
be cleared to disable the clock to any of these modules when not in use. See Section 5.6, “Peripheral Clock
Gating,” for details.
17.1.3 Interrupt Vector
See Chapter 8, “Interrupt Controller (CF1_INTC),” for the TPM interrupt vector assignments.