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MCF51QE128 MCU Series Reference Manual, Rev. 3
Freescale Semiconductor 123
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Chapter 6 Parallel Input/Output Control
6.7.2.5 Port B Drive Strength Selection Register (PTBDS)
6.7.3 Port C Registers
Port C is controlled by the registers listed below.
6.7.3.1 Port C Data Register (PTCD)
76543210
R
PTBDS7 PTBDS6 PTBDS5 PTBDS4 PTBDS3 PTBDS2 PTBDS1 PTBDS0
W
Reset:00000000
Figure 6-13. Drive Strength Selection for Port B Register (PTBDS)
Table 6-10. PTBDS Register Field Descriptions
Field Description
7–0
PTBDSn
Output Drive Strength Selection for Port B Bits. Each of these control bits selects between low and high output
drive for the associated PTB pin. For port B pins configured as inputs, these bits have no effect.
0 Low output drive strength selected for port B bit n.
1 High output drive strength selected for port B bit n.
76543210
R
PTCD7 PTCD6 PTCD5 PTCD4 PTCD3 PTCD2 PTCD1 PTCD0
W
Reset:00000000
Figure 6-14. Port C Data Register (PTCD)
Table 6-11. PTCD Register Field Descriptions
Field Description
7–0
PTCDn
Port C Data Register Bits. For port C pins configured as inputs, reads return the logic level on the pin. For port
C pins configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port C pins configured as outputs, the logic level is driven out
the corresponding MCU pin.
Reset forces PTCD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups disabled.