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MCF51QE128 MCU Series Reference Manual, Rev. 3
298 Freescale Semiconductor
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15.2 Register Definition
The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for
transmit/receive data.
Refer to the direct-page register summary in the memory chapter of this document or the absolute address
assignments for all SCI registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
15.2.1 SCI Baud Rate Registers (SCIxBDH, SCIxBDL)
This pair of registers controls the prescale divisor for SCI baud rate generation. To update the 13-bit baud
rate setting [SBR12:SBR0], first write to SCIxBDH to buffer the high half of the new value and then write
to SCIxBDL. The working value in SCIxBDH does not change until SCIxBDL is written.
SCIxBDL is reset to a non-zero value, so after reset the baud rate generator remains disabled until the first
time the receiver or transmitter is enabled (RE or TE bits in SCIxC2 are written to 1).
76543210
R
LBKDIE RXEDGIE
0
SBR[12:8]
W
Reset00000000
Figure 15-5. SCI Baud Rate Register (SCIxBDH)
Table 15-1. SCIxBDH Field Descriptions
Field Description
7
LBKDIE
LIN Break Detect Interrupt Enable (for LBKDIF)
0 Hardware interrupts from LBKDIF disabled (use polling).
1 Hardware interrupt requested when LBKDIF flag is 1.
6
RXEDGIE
RxD Input Active Edge Interrupt Enable (for RXEDGIF)
0 Hardware interrupts from RXEDGIF disabled (use polling).
1 Hardware interrupt requested when RXEDGIF flag is 1.
4–0
SBR[12:8]
Baud Rate Modulo Divisor. The 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo
divide rate for the SCI baud rate generator. When BR is cleared, the SCI baud rate generator is disabled to
reduce supply current. When BR is 1 – 8191, the SCI baud rate equals BUSCLK/(16×BR). See also BR bits in
Ta bl e 1 5- 2.
76543210
R
SBR[7:0]
W
Reset00000100
Figure 15-6. SCI Baud Rate Register (SCIxBDL)