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RL78/G1A
CHAPTER 30 ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS T
A
=
−
40 to +105
°
C)
R01UH0305EJ0200 Rev.2.00 941
Jul 04, 2013
(8) Communication at different potential (1.8 V, 2.5 V) (simplified I
2
C mode) (2/2)
(T
A = −40 to +105°C, 2.4 V ≤ EVDD0 ≤ VDD ≤ 3.6 V, VSS = EVSS0 = 0 V)
Parameter Symbol Conditions MIN. MAX. Unit
2.7 V ≤ EVDD0 ≤ 3.6 V,
2.3 V ≤ V
b ≤ 2.7 V,
C
b = 50 pF, Rb = 2.7 kΩ
1/f
MCK +
340
Note 2
ns
2.7 V ≤ EVDD0 ≤ 3.6 V,
2.3 V ≤ V
b ≤ 2.7 V,
C
b = 100 pF, Rb = 2.7 kΩ
1/f
MCK +
760
Note 2
ns
Data setup time (reception) tSU:DAT
2.4 V ≤ EV
DD0 < 3.3 V,
1.6 V ≤ V
b ≤ 2.0 V,
C
b = 100 pF, Rb = 5.5 kΩ
1/f
MCK +
570
Note 2
ns
2.7 V ≤ EVDD0 ≤ 3.6 V,
2.3 V ≤ V
b ≤ 2.7 V,
C
b = 50 pF, Rb = 2.7 kΩ
0 770 ns
2.7 V ≤ EVDD0 ≤ 3.6 V,
2.3 V ≤ V
b ≤ 2.7 V,
C
b = 100 pF, Rb = 2.7 kΩ
0 1420 ns
Data hold time (transmission) tHD:DAT
2.4 V ≤ EV
DD0 < 3.3 V,
1.6 V ≤ V
b ≤ 2.0 V,
C
b = 100 pF, Rb = 5.5 kΩ
0 1215 ns
Notes 1. The value must also be f
CLK/4 or lower.
2. Set the fMCK value to keep the hold time of SCLr = “L” and SCLr = “H”.
Caution Select the TTL input buffer and the N-ch open drain output (V
DD tolerance (When 25- to 48-pin
products)/EVDD tolerance (When 64-pin products)) mode for the SDAr pin and the N-ch open drain
output (V
DD tolerance (When 25- to 48-pin products)/EVDD tolerance (When 64-pin products)) mode for
the SCLr pin by using port input mode register g (PIMg) and port output mode register g (POMg). For
V
IH and VIL, see the DC characteristics with TTL input buffer selected.
(Remarks are listed on the next page.)
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