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RL78/G1A CHAPTER 6 TIMER ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 238
Jul 04, 2013
Caution While timer output is enabled (TOEmn = 1), even if the output by timer interrupt of each timer
(INTTMmn) contends with writing to the TOmn bit, output is normally done to the TOmn pin.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3 to 7)
6.6.5 Timer interrupt and TOmn pin output at operation start
In the interval timer mode or capture mode, the MDmn0 bit in timer mode register mn (TMRmn) sets whether or not to
generate a timer interrupt at count start.
When MDmn0 is set to 1, the count operation start timing can be known by the timer interrupt (INTTMmn) generation.
In the other modes, neither timer interrupt at count operation start nor TOmn output is controlled.
Figure
6-38 shows operation examples when the interval timer mode (TOEmn = 1, TOMmn = 0) is set.
Figure 6-38. Operation Examples of Timer Interrupt at Count Operation Start and TOmn Output
(a) When MDmn0 is set to 1
TCRmn
TEmn
TOmn
INTTMmn
Count operation start
(b) When MDmn0 is set to 0
TCRmn
TEmn
TOmn
INTTMmn
Count operation start
When MDmn0 is set to 1, a timer interrupt (INTTMmn) is output at count operation start, and TOmn performs a toggle
operation.
When MDmn0 is set to 0, a timer interrupt (INTTMmn) is not output at count operation start, and TOmn does not
change either. After counting one cycle, INTTMmn is output and TOmn performs a toggle operation.
Remark m: Unit number (m = 0), n: Channel number (n = 0, 1, 3 to 7)