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RL78/G1A CHAPTER 6 TIMER ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 290
Jul 04, 2013
Figure 6-79. Operation Procedure When Multiple PWM Output Function Is Used (2/2)
Software Operation Hardware Status
Operation
start
(Sets the TOEmp and TOEmq (slave) bits to 1 only when
resuming operation.)
The TSmn bit (master), and TSmp and TSmq (slave) bits
of timer channel start register m (TSm) are set to 1 at the
same time.
The TSmn, TSmp, and TSmq bits automatically return
to 0 because they are trigger bits.
TEmn = 1, TEmp, TEmq = 1
When the master channel starts counting, INTTMmn is
generated. Triggered by this interrupt, the slave
channel also starts counting.
During
operation
Set values of the TMRmn, TMRmp, TMRmq registers,
TOMmn, TOMmp, TOMmq, TOLmn, TOLmp, and TOLmq
bits cannot be changed.
Set values of the TDRmn, TDRmp, and TDRmq registers
can be changed after INTTMmn of the master channel is
generated.
The TCRmn, TCRmp, and TCRmq registers can always
be read.
The TSRmn, TSRmp, and TSR0q registers are not used.
The counter of the master channel loads the TDRmn
register value to timer count register mn (TCRmn) and
counts down. When the count value reaches TCRmn =
0000H, INTTMmn output is generated. At the same time,
the value of the TDRmn register is loaded to the TCRmn
register, and the counter starts counting down again.
At the slave channel 1, the values of the TDRmp register
are transferred to the TCRmp register, triggered by
INTTMmn of the master channel, and the counter starts
counting down. The output levels of TOmp become active
one count clock after generation of the INTTMmn output
from the master channel. It becomes inactive when
TCRmp = 0000H, and the counting operation is stopped.
At the slave channel 2, the values of the TDRmq register
are transferred to TCRmq regster, triggered by INTTMmn
of the master channel, and the counter starts counting
down. The output levels of TOmq become active one
count clock after generation of the INTTMmn output from
the master channel. It becomes inactive when TCRmq =
0000H, and the counting operation is stopped.
After that, the above operation is repeated.
The TTmn bit (master), TTmp, and TTmq (slave) bits are
set to 1 at the same time.
The TTmn, TTmp, and TTmq bits automatically return
to 0 because they are trigger bits.
TEmn, TEmp, TEmq = 0, and count operation stops.
The TCRmn, TCRmp, and TCRmq registers hold count
value and stop.
The TOmp and TOmq output are not initialized but hold
current status.
Operation
stop
The TOEmp and TOEmq bits of slave channels are
cleared to 0 and value is set to the TOmp and TOmq bits.
The TOmp and TOmq pins output the TOmp and TOmq
set levels.
To hold the TOmp and TOmq pin output levels
Clears the TOmp and TOmq bits to 0 after
the value to be held is set to the port register.
When holding the TOmp and TOmq pin output levels are
not necessary
Setting not required
The TOmp and TOmq pin output levels are held by port
function.
TAU
stop
The TAUmEN bit of the PER0 register is cleared to 0.
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
(The TOmp and TOmq bits are cleared to 0 and the
TOmp and TOmq pins are set to port mode.)
Remark m: Unit number (m = 0), n: Channel number (n = 0, 2, 4)
p: Slave channel number 1, q: Slave channel number 2
n < p < q ≤ 7
However, timer output pin (TOmp, TOmq) : p = 1, 3 to 6, q = 3 to 7
Operation is resumed.