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RL78/G1A CHAPTER 21 VOLTAGE DETECTOR
21.3.2 Voltage detection level register (LVIS)
This register selects the voltage detection level.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation input sets this register to 00H/01H/81H
Note 1
.
Figure 21-3. Format of Voltage Detection Level Select Register (LVIS)
Address: FFFAAH After reset: 00H/01H/81H
Note 1
R/W
Symbol <7> 6 5 4 3 2 1 <0>
LVIS LVIMD 0 0 0 0 0 0 LVILV
LVIMD
Note 2
Operation mode of voltage detection
0 Interrupt mode
1 Reset mode
LVILV
Note 2
LVD detection level
0 High-voltage detection level (VLVDH)
1 Low-voltage detection level (VLVDL or VLVDL)
Notes 1. The reset value changes depending on the reset source and the setting of the option byte.
This register is not cleared (00H) by LVD reset.
The generation of reset signal other than an LVD reset sets as follows.
• When option byte LVIMDS1, LVIMDS0 = 1, 0: 00H
• When option byte LVIMDS1, LVIMDS0 = 1, 1: 81H
• When option byte LVIMDS1, LVIMDS0 = 0, 1: 01H
2. Writing “0” can only be allowed in the interrupt & reset mode (option byte LVIMDS1, LVIMDS0 = 1, 0). Do
not set LVIMD and LVILV in other cases. The value is switched automatically when reset or interrupt is
generated in the interrupt & reset mode.
<R>
Cautions 1. Rewrite the value of the LVIS register according to Figures 21-7 and 21-8.
<R>
2. Specify the LVD operation mode and detection voltage (V
LVDH, VLVDL, VLVD) of each mode by
using the option byte 000C1H. Table 21-1 shows the format of the user option byte
(000C1H/010C1H). For details about the option byte, see CHAPTER 24 OPTION BYTE.
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R01UH0305EJ0200 Rev.2.00 757
Jul 04, 2013