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RL78/G1A CHAPTER 6 TIMER ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 274
Jul 04, 2013
Figure 6-69. Operation Procedure of One-Shot Pulse Output Function (1/2)
Software Operation Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAUmEN bit of peripheral enable registers 0
(PER0) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
TAU
default
setting
Sets timer clock select register m (TPSm).
Determines clock frequencies of CKm0 and CKm1.
Sets corresponding bit of noise filter enable register 1
(NFEN1) to 0 (OFF) or 1 (ON).
Sets timer mode register mn, mp (TMRmn, TMRmp) of
two channels to be used (determines operation mode of
channels).
An output delay is set to timer data register mn (TDRmn)
of the master channel, and a pulse width is set to the
TDRmp register of the slave channel.
Channel stops operating.
(Clock is supplied and some power is consumed.)
Channel
default
setting
Sets slave channel.
The TOMmp bit of timer output mode register m
(TOMm) is set to 1 (slave channel output mode).
Sets the TOLmp bit.
Sets the TOmp bit and determines default level of the
TOmp output.
Sets the TOEmp bit to 1 and enables operation of TOmp.
Clears the port register and port mode register to 0.
The TOmp pin goes into Hi-Z output state.
The TOmp default setting level is output when the port
mode register is in output mode and the port register is 0.
TOmp does not change because channel stops operating.
The TOmp pin outputs the TOmp set level.
(Note and Remark are listed on the next page.)
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