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RL78/G1A CHAPTER 11 A/D CONVERTER
R01UH0305EJ0200 Rev.2.00 366
Jul 04, 2013
11.3.8 Conversion result comparison upper limit setting register (ADUL)
This register is used to specify the setting for checking the upper limit of the A/D conversion results.
The A/D conversion results and ADUL register value are compared, and A/D conversion end interrupt request signal
(INTAD) generation is controlled in the range specified for the ADRCK bit of A/D converter mode register 2 (ADM2)
(shown in Figure 11-8).
The ADUL register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Figure 11-12. Format of Conversion Result Comparison Upper Limit Setting Register (ADUL)
Address: F0011H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
ADUL ADUL7 ADUL6 ADUL5 ADUL4 ADUL3 ADUL2 ADUL1 ADUL0
11.3.9 Conversion result comparison lower limit setting register (ADLL)
This register is used to specify the setting for checking the lower limit of the A/D conversion results.
The A/D conversion results and ADLL register value are compared, and A/D conversion end interrupt request signal
(INTAD) generation is controlled in the range specified for the ADRCK bit of A/D converter mode register 2 (ADM2)
(shown in Figure 11-8).
The ADLL register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 11-13. Format of Conversion Result Comparison Lower Limit Setting Register (ADLL)
Address: F0012H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
ADLL ADLL7 ADLL6 ADLL5 ADLL4 ADLL3 ADLL2 ADLL1 ADLL0
Cautions 1. When 12-bit resolution A/D conversion is selected, the higher eight bits of the 12-bit A/D
conversion result register (ADCR) are compared with the ADUL register and ADLL register.
2. Only rewrite the value of the ADUL register and ADLL register while conversion operation is
stopped (which is indicated by the ADCE bit of A/D converter mode register 0 (ADM0) being 0).
3. Make sure that ADUL > ADLL when setting these registers.