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RL78/G1A CHAPTER 7 REAL-TIME CLOCK
Figure 7-5. Format of Real-time Clock Control Register 1 (RTCC1) (2/2)
Address: FFF9EH After reset: 00H R/W
Symbol <7> <6> 5 <4> <3> 2 <1> <0>
RTCC1 WALE WALIE 0 WAFG RIFG 0 RWST RWAIT
RWST Wait status flag of real-time clock
0 Counter is operating.
1 Mode to read or write counter value
This status flag indicates whether the setting of the RWAIT bit is valid.
Before reading or writing the counter value, confirm that the value of this flag is 1.
RWAIT Wait control of real-time clock
0 Sets counter operation.
1 Stops SEC to YEAR counters. Mode to read or write counter value
This bit controls the operation of the counter.
Be sure to write “1” to it to read or write the counter value.
As the internal counter (16-bit) is continuing to run, complete reading or writing within one second and turn back to
0.
When RWAIT = 1, it takes up to one cycle of f
RTC until the counter value can be read or written (RWST = 1).
When the internal counter (16-bit) overflowed while RWAIT = 1, it keeps the event of overflow until RWAIT = 0, then
counts up.
However, when it wrote a value to second count register, it will not keep the overflow event.
Caution If writing is performed to the RTCC1 register with a 1-bit manipulation instruction, the RIFG flag
and WAFG flag may be cleared. Therefore, to perform writing to the RTCC1 register, be sure to
use an 8-bit manipulation instruction. To prevent the RIFG flag and WAFG flag from being
cleared during writing, disable writing by setting 1 to the corresponding bit. If the RIFG flag and
WAFG flag are not used and the value may be changed, the RTCC1 register may be written by
using a 1-bit manipulation instruction.
Remarks 1. Fixed-cycle interrupts and alarm match interrupts use the same interrupt source (INTRTC). When
using these two types of interrupts at the same time, which interrupt occurred can be judged by
checking the fixed-cycle interrupt status flag (RIFG) and the alarm detection status flag (WAFG) upon
INTRTC occurrence.
2. The internal counter (16 bits) is cleared when the second count register (SEC) is written.
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R01UH0305EJ0200 Rev.2.00 300
Jul 04, 2013