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RL78/G1A CHAPTER 6 TIMER ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 210
Jul 04, 2013
6.3.8 Timer input select register 0 (TIS0)
The TIS0 register is used to select the channel 5 of unit 0 timer input..
The TIS0 register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 6-16. Format of Timer Input Select register 0 (TIS0)
Address: F0074H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
TIS0 0 0 0 0 0 TIS02 TIS01 TIS00
TIS02 TIS01 TIS00 Selection of timer input used with channel 5
0 0 0
0 0 1
0 1 0
0 1 1
Input signal of timer input pin (TI05)
1 0 0 Low-speed on-chip oscillator clock (fIL)
1 0 1 Subsystem clock (fSUB)
Other than above Setting prohibited
Caution High-level width, low-level width of timer input is selected, will require more than 1/f
MCK +10 ns.
Therefore, when selecting f
SUB to fCLK (CSS bit of CKS register = 1), can not TIS02 bit set to 1.