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RL78/G1A CHAPTER 15 DMA CONTROLLER
15.6 Cautions on Using DMA Controller
(1) Priority of DMA
During DMA transfer, a request from the other DMA channel is held pending even if generated. The pending DMA
transfer is started after the ongoing DMA transfer is completed. If two or more DMA requests are generated at the
same time, however, their priority are DMA channel 0 > DMA channel 1.
If a DMA request and an interrupt request are generated at the same time, the DMA transfer takes precedence,
and then interrupt servicing is executed.
(2) DMA response time
The response time of DMA transfer is as follows.
Table 15-3. Response Time of DMA Transfer
Minimum Time Maximum Time
10 clocks
Note
Response time
3 clocks
Note The maximum time necessary to execute an instruction from internal RAM is 16 clock cycles.
Cautions 1. The above response time does not include the two clock cycles required for a DMA
transfer.
2. When executing a DMA pending instruction (see 15.6 (4)), the maximum response
time is extended by the execution time of that instruction to be held pending.
3. Do not specify successive transfer triggers for a channel within a period equal to the
maximum response time plus one clock cycle, because they might be ignored.
Remark 1 clock: 1/f
CLK (fCLK: CPU clock)
(3) Operation in standby mode
The DMA controller operates as follows in the standby mode.
Table 15-4. DMA Operation in Standby Mode
Status DMA Operation
HALT mode Normal operation
Stops operation.
If DMA transfer and STOP instruction execution contend, DMA transfer may be
damaged. Therefore, stop DMA before executing the STOP instruction.
STOP mode
R01UH0305EJ0200 Rev.2.00 685
Jul 04, 2013