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RL78/G1A CHAPTER 12 SERIAL ARRAY UNIT
R01UH0305EJ0200 Rev.2.00 521
Jul 04, 2013
Figure 12-88. Flowchart of UART Reception
Starting UART communication
Interrupt (mask)
End of UART
Reception completed?
No
Yes
No
Yes
Error processing
Writing 1 to the STmn bit
Enables interrupt
Clear interrupt request flag (XXIF), reset interrupt mask
(XXMK) and set
Wait for receive completes
Starting reception if start bit is
detected
When receive complete, transfer end
interrupt is generated.
Transfer end interrupt
Indicating normal reception?
Reading receive data from
the SDRmn[7:0] bits
(RXDq register) (8 bits) or
the SDRmn[8:0] bits (9 bits)
Read receive data then writes to storage area.
Update receive data pointer and number of
communication data.
RETI
SAU default setting
Setting storage area of the receive data, number of communication
data (storage area, reception data pointer, number of communication
data and communication end flag are optionally set on the internal
RAM by the software)
Setting receive data
Check the number of communication data,
determine the completion of reception
Main routine
Interrupt processing routine
For the initial setting, see Figure 12-85.
(setting to mask for error interrupt)
Main routine
Remark m: Unit number (m = 0, 1), n: Channel number (n = 1, 3), mn = 01, 03, 11
r: Channel number (r = n − 1), q: UART number (q = 0 to 2)
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